한국마이크로전자및패키징학회:학술대회논문집 (Proceedings of the International Microelectronics And Packaging Society Conference)

한국마이크로전자및패키징학회 (The Korean Microelectronics and Packaging Society)
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$(Bi,La)Ti_3O_{12}$ 강유전체 박막 게이트를 갖는 전계효과 트랜지스터 소자의 제작

Preparation of Field Effect Transistor with $(Bi,La)Ti_3O_{12}$ Ferroelectric Thin Film Gate

  • 서강모 (단국대학교 전자컴퓨터공학과) ;
  • 박지호 (단국대학교 전자컴퓨터공학과) ;
  • 공수철 (단국대학교 전자컴퓨터공학과) ;
  • 장호정 (단국대학교 전자컴퓨터공학과) ;
  • 장영철 (한국기술교육대학교 메카트로닉스공학부) ;
  • 심선일 (한국과학기술연구원 반도체소자연구실) ;
  • 김용태 (한국과학기술연구원 반도체소자연구실)
  • Suh Kang Mo (Electronics and Computer Engineering, Dankook University) ;
  • Park Ji Ho (Electronics and Computer Engineering, Dankook University) ;
  • Gong Su Cheol (Electronics and Computer Engineering, Dankook University) ;
  • Chang Ho Jung (Electronics and Computer Engineering, Dankook University) ;
  • Chang Young Chul (School of Mechatronics Engineering, Korea University of Technology and Education) ;
  • Shim Sun Il (Semiconductor Materials and Devices Lab, Korea Institute of Science and Technology) ;
  • Kim Yong Tae (Semiconductor Materials and Devices Lab, Korea Institute of Science and Technology)
  • 발행 : 2003.11.01
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초록

The MFIS-FET(Field Effect Transistor) devices using $BLT/Y_2O_3$ buffer layer on p-Si(100) substrates were fabricated by the Sol-Gel method and conventional memory processes. The crystal structure, morphologies and electrical properties of prepared devices were investigated by using various measuring techniques. From the C-V(capacitance-voltage) data at 5V, the memory window voltage of the $Pt/BLT/Y_2O_3/si$ structure decreased from 1.4V to 0.6V with increasing the annealing temperature from $700^{\circ}C\;to\;750^{\circ}C$. The drain current (Ic) as a function of gate voltages $(V_G)$ for the $MFIS(Pt/BLT/Y_2O_3/Si(100))-FET$ devices at gate voltages $(V_G)$ of 3V, 4V and 5V, the memory window voltages increased from 0.3V to 0.8V as $V_G$ increased from 3V to 5V.

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