Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference (한국전기전자재료학회:학술대회논문집)
- 2003.07b
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- Pages.1188-1191
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- 2003
A Study on the Design of PLL for Improving of Characteristics of Locking Time and Jitter
Locking Time과 Jitter 특성의 개선을 위한 PLL 설계에 관한 연구
- Park, Jae-Boum (Korea Univ.) ;
- Park, Yun-Sik (Korea Univ.) ;
- Kim, Hwa-Young (Korea Univ.) ;
- Sung, Man-Young (Korea Univ.)
- Published : 2003.07.10
Abstract
In this paper, we focus our attention on the improvement of locking time and jitter parameter and propose the new structure of PLL which combined with the FVC, FOVI Matcher(FVC-Output and VCO-input Matching Circuit), Control Circuit and the conventional charge pump PLL. Using fast operation characteristics of the FVC, the circuit matching FVC-Output and VCO-input (FOVI Matcher) made to synchronize very fast. Fast locking time is usually required for application where the PLL has to settle rapidly if they switch from an idle mode to a normal mode and to track high-frequency data bit rate in data recovery systems. After a fast acqusition is achieved by the using the FVC, the conventional PLL operates for removing the phase error between the reference signal and the feedback signal. Therefore this structure can improve the trade-off between acquisition behavior and locked behavior.