Gate Freezing, Gate Sizing, and Buffer Insertion for reducing Glitch Power Dissipation

단일화된 게이트 프리징, 사이징 및 버퍼삽입에 의한 저 전력 최적화 알고리즘

We present an efficient heuristic algorithm to reduce glitch power dissipation in combinational circuits. In this paper, the total number of glitches are reduced by replacing existing gates with functionally equivalent ones and by gate sizing which classified into three types and by buffer insertion which classified into two types. The proposed algorithm combines gate freezing, gate sizing. and buffer insertion into a single optimization process to maximize the glitch reduction. Our experimental results show an average of $67.8\%$ glitch reduction and $32.0\%$ power reduction by simultaneous gate freezing, gate sizing, and buffer insertion.