Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference (한국전기전자재료학회:학술대회논문집)
- 2004.07a
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- Pages.224-226
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- 2004
Issues in CMP Technology and Future Challenges for Sub-100nm Devices
100nm 이하 Device에서의 CMP 기술의 문제점 및 향후 도전과제
- Yun, Seong-Kyu (Semiconductor R&D Center, Samsung Electronics Co.,Ltd) ;
- Lee, Jae-Dong (Semiconductor R&D Center, Samsung Electronics Co.,Ltd) ;
- Hong, Chang-Ki (Semiconductor R&D Center, Samsung Electronics Co.,Ltd) ;
- Cho, Han-Ku (Semiconductor R&D Center, Samsung Electronics Co.,Ltd) ;
- Moon, Joo-Tae (Semiconductor R&D Center, Samsung Electronics Co.,Ltd) ;
- Ryu, Byoung-Il (Semiconductor R&D Center, Samsung Electronics Co.,Ltd)
- 윤성규 (삼성전자 반도체연구소) ;
- 이재동 (삼성전자 반도체연구소) ;
- 홍창기 (삼성전자 반도체연구소) ;
- 조한구 (삼성전자 반도체연구소) ;
- 문주태 (삼성전자 반도체연구소) ;
- 류병일 (삼성전자 반도체연구소)
- Published : 2004.07.05
Abstract
CMP process requirements become tighter especially in sub-100nm technology. Especially, high planarity and low defectivity appear as leading issues in CMP technology. Also, the introduction of new materials and advanced lithography technique increases CMP applications. Here are listed some major issues and challenges in CMP technology, which can be categorized following four items. These have practical significance and should be considered more concretely for future generation.