CMOS 공정을 이용한 높은 선형성을 갖는 900MHz RFID 용 LNA

A High Linearity 900-MHz CMOS LNA for RFID

In this paper, we present a design procedure of high linearity LNA using CMOS technology. To enhance the low linearity of the inherent CMOS transistor, we adopt the modified derivate superposition with adding external capacitor. The simulation of the designed LNA shows $IIP_3$ of +12-dBm, power gain of 13.8-dB, noise figure of 1.75-dB over the 900 MHz UHF RFID frequencies. The circuit draws the current of 4.2 mA from 1.8-V supply voltage.