대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

$0.35{\mu}m$ CMOS 공정을 이용한 $32{\times}32$ IRFPA ROIC용 Folded-Cascode Op-Amp 설계

Folded-Cascode Operational Amplifier for $32{\times}32$ IRFPA Readout Integrated Circuit using the $0.35{\mu}m$ CMOS process

  • 김소희 (인제대학교 나노공학부) ;
  • 이효연 (인제대학교 나노공학부) ;
  • 정진우 (인제대학교 나노공학부) ;
  • 김진수 (인제대학교 나노공학부) ;
  • 강명훈 (인제대학교 나노공학부) ;
  • 박용수 (충청대학 전기전자공학부) ;
  • 송한정 (인제대학교 나노공학부) ;
  • 전민현 (인제대학교 나노공학부)
  • 발행 : 2007.07.11
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초록

The IRFPA (InfraRed Focal Plane Array) ROIC (ReadOut Integrated Circuit) was designed in folded-cascode Op-Amp using $0.35{\mu}m$ CMOS technology. As the folded-cascode has high open-loop voltage gain and fast settling time, that used in many analog circuit designs. In this paper, folded-cascode Op-Amp for ROIC of the $32{\times}32$ IRFPA has been designed. HSPICE simulation results are unit gain bandwidth of 13.0MHz, 90.6 dB open loop gain, 8 V/${\mu}m$ slew rate, 600 ns settling time and $66^{\circ}$ phase margin.

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