Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference (한국전기전자재료학회:학술대회논문집)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Electrical characteristic of stacked $SiO_2/ZrO_2$ for nonvolatile memory application as gate dielectric

비휘발성 메모리 적용을 위한 $SiO_2/ZrO_2$ 다층 유전막의 전기적 특성

  • Park, Goon-Ho (Department of Electronic materia1s engineering, Kwangwoon Univ.) ;
  • Kim, Kwan-Su (Department of Electronic materia1s engineering, Kwangwoon Univ.) ;
  • Oh, Jun-Seok (Department of Electronic materia1s engineering, Kwangwoon Univ.) ;
  • Jung, Jong-Wan (Department of Nano Science and Technology, Sejong Univ.) ;
  • Cho, Won-Ju (Department of Electronic materia1s engineering, Kwangwoon Univ.)
  • Published : 2008.06.19
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Abstract

Ultra-thin $SiO_2/ZrO_2$ dielectrics were deposited by atomic layer chemical vapor deposition (ALCVD) method for non-volatile memory application. Metal-oxide-semiconductor (MOS) capacitors were fabricated by stacking ultra-thin $SiO_2$ and $ZrO_2$ dielectrics. It is found that the tunneling current through the stacked dielectric at the high voltage is lager than that through the conventional silicon oxide barrier. On the other hand, the tunneling leakage current at low voltages is suppressed. Therefore, the use of ultra-thin $SiO_2/ZrO_2$ dielectrics as a tunneling barrier is promising for the future high integrated non-volatile memory.

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