Layer Assignment of Functional Chip Blocks for 3-D Hybrid IC Planning

3차원 Hybrid IC 배치를 위한 기둥첩 블록의 층할당

Traditional circuit partitioning algorithm using the cluster development method, which is suitable for such applications as single chip floor planning or multiple layer PCB system placement, where the clusters are formed so that inter-cluster nets are localized within the I/O connector pins, may not be appropriate for the functiona block placement in truly 3-D electronic modules. 3-D hybrid IC is one such example where the inter-layer routing as well as the intra-layer routing can be maximally incorporated to reduce the overall circuit size, cooling requirements and to improve the speed performance. In this paper, we propose a new algorithm called MBE(Minimum Box Embedding) for the layer assignment of each functional block in 3-D hybrid IC design. The sequence of MBE is as follows` i) force-directed relaxation in 3-D space, ii) exhaustive search for the optimal orientation of the slicing plane and iii) layer assignment. The algorithm is first explaines for a 2-D reduced problem, and then extended for 3-D applications. An example result for a circuit consisting of 80 blocks has been shown.