전자공학회논문지A (Journal of the Korean Institute of Telematics and Electronics A)
- 제31A권2호
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- Pages.116-124
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- 1994
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- 1016-135X(pISSN)
비동기 인터페이스를 지원하는 정원 수준 합성 시스템의 설계
Design of a High-Level Synthesis System Supporting Asynchronous Interfaces
초록
This paper describes the design of a high-level synthesis system. ISyn: Interface Synthesis System for ISPS-A. which generates hardware satisfying timing constraints. The original version of ISPS is extended to be used for the description/capture of interface operations and timing constraints in the ISPS-A. To generate the schedule satisfying interface constraints the scheduling process is divided into two steps:pre-scheduling and post-scheduling. ISyn allocates hardware modules with I/O ports by the clique partitioning algorithm. Experimental results show that ISyn is capable of synthesizing hardware modules effectively for internal and/or interactive operations.
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