Design of a high-speed 32-bit adder using a new dynamic CMOS logic

새로운 동적 CMOS 논리 설계방식을 이용한 고성능 32비트 가산기 설계

This paper proposes two new dynamic CMOS logic styles, called ZMODL (zipper-MODL) and EZMODL (enhanced-ZMODL), which can reduce more area dnd propagation delya than conventional MODL (multiple output domino logic). The 32-bit CLAs(carry look-ahead adder) are designed by ZMODL, EZMODL circuits, and their operations are verified by SPICE 3 with 2$\mu$ double metal CMOS parameters. The results shwo that the CLA designed by EZMODL circuit has achived 32-bit additin time of less than 4.8NS with VDD=5.0V and 8% of transistors cn be redcued, compared to the CLA designed by MODL. The EZMODL logic style can improve the performance in the high-speed computing circuits depending on the degree of recurrence.