The design of high-accuracy CMOS sampel-and-hold amplifiers

고정밀 CMOS sample-and-hold 증폭기 설계 기법 및 성능 비교

The accuracy of sample-and-hold amplifiers (SHA's) empolying a CMOS process in limited by nonideal factors such as linearity errors of an op amp and feedthrough errors of switches. In this work, after some linearity improvement techniques for an op amp are discussed, three different SHA's for video signal processing are designed, simulated, and compared. The CMOS SHA design techniques with a 12-bit level accuracy are proposed by minimizing cirucit errors based on the simulated results.