ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Design and Characterization of a 10 Gb/s Clock and Data Recovery Circuit Implemented with Phase-Locked Loop

  • Received : 1999.04.09
  • Published : 1999.09.30
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Abstract

A clock and data recovery circuit with a phase-locked loop for 10 Gb/s optical transmission system was realized in a hybrid IC form. The quadri-correlation architecture is used for frequency-and phase-locked loop. A NRZ-to-PRZ converter and a 360 degree analogue phase shifter are included in the circuit. The jitter characteristics satisfy the recommendations of ITU-T. The capture range of 150 MHz and input voltage sensitivity of 100 mVp-p were showed. The temperature compensation characteristics were tested for the operating temperature from -10 to $60^{\circ}C$ and showed no increase of error. This circuit was adopted for the 10 Gb/s transmission system through a normal single-mode fiber with the length of 400 km and operated successfully.

Keywords

References

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