대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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고속 메모리동작을 위한 디지털 DLL회로 설계

A Design of Digital DLL Circuits For High-Speed Memory

  • 이중호 (現大電子 메모리 硏究所) ;
  • 조상복 (蔚産大學校 電氣電子 및 自動化 工學部)
  • Lee, Joong-Ho (Hyundai Electronic Memory Research Center Design Team) ;
  • Cho, Sang-Bock (School of Electronic, Electronics and Automation, University of Ulsan)
  • 발행 : 2000.07.01
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 DDR(Double Data Rate) Synchronous DRAM에서 안전한 데이터 영역(tDV) 확보를 위한 DDL(Delay Locked Loop) 회로인 ADD(Alternate Directional Delay)회로 방식을 제안하였다. 본 방식은 디지털 DLL의 단점인 부가회로 면적(area-overhead)을 절감할 수 있는 방식으로ㅆ, 하나의 지연회로 체인(chain)을 이용하여 동시에 양방향으로 클럭을 발생할 수 있도록 함으로써 기존의 SMD(Synchronous Mirror Delay)방식에 비해 약 2배의 부가회로 면적을 감소할 수 있도록 설계하였다. 또한 설계한 ADD방식이 지터(jitter)는 50ps-140ps이고, 동ㅈ가 주파수 영역은 166MHz-66MHz이다.(205V, TYP, 동작조건)

We proposed ADD(Alternate Directional Delay) circuit technique as the DLL(Delay Locked Loop) circuits which technique is established the data valid window(tDV) in DDR(Double Data Rate) Synchronous DRAM. This technique could be decrease area-overhead which it could generated bidirectional clock simultaneously using only one delay chain block. In this paper for high speed memory with relatively small size. This technique decreased area-overhead more 2 times than SMD(Synchronous Mirror Delay) technique. ADD technique has 50ps-140ps jitter and the operation frequency has 166MHz-66MHz range.(at 2.5V, TYP. condition)

키워드

참고문헌

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