대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

마이크로파이프라인 회로를 위한 지연 고장 테스트

Path Delay Testing for Micropipeline Circuits

  • 강용석 (延世大學校 電氣電子工學科) ;
  • 허경회 (延世大學校 電氣電子工學科) ;
  • 강성호 (延世大學校 電氣電子工學科)
  • Kang, Yong-Seok (Dept. of Electrical & Electronic Eng. Yonsei University) ;
  • Huh, Kyung-Hoi (Dept. of Electrical & Electronic Eng. Yonsei University) ;
  • Kang, Sung-Ho (Dept. of Electrical & Electronic Eng. Yonsei University)
  • 발행 : 2001.08.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

마이크로파이프라인 회로의 모든 연산 소자의 타이밍은 아주 중요하다. 스캔 플립플롭을 이용한 경로 지연고장 테스팅에 관한 기존 연구들은 두 개의 테스트 패턴 중 두 번째 패턴의 조절용이도가 높아야 한다는 점을 간과하였다. 본 논문에서는 작은 면적 오버헤드로 마이크로파이프라인 회로의 경로 지연고장을 테스트 할 수 있는 새로운 스캔 래치 및 테스트 방법을 제안하였다. 새로운 스캔 래치를 사용하여 마이크로파이프라인의 경로지연고장을 테스트한 결과에서 기존연구에 비해 높은 경성 경로 지연고장 검출율을 얻었다. 또한 제안된 스캔 래치는 마이크로파이프라인의 고착고장 검출을 위한 BIST로 응용을 확대하기 쉽다.

The timings of all computational elements in the micropipeline circuits are important. The previous researches on path delay testing using scan methods make little account of the characteristic of the path delay tests that the second test pattern must be more controllable. In this paper, a new scan latch is proposed which is suitable to path delay testing of the micropipelines and has small area overhead. Results show that path delay faults in the micropipeline circuits using the new scan are testable robustly and the fault coverage is higher than the previous researches. In addition, the new scan latch for path delay faults testing in the micropipeline circuits can be easily expanded to the applications such as BIST for stuck-at faults.

키워드

참고문헌

  1. A. Martin. 'From Communicating processes to delay-insensitive circuits,' Technical report, Dept. of Computer Science, Caltech, 1989
  2. P. A. Beerel and T. H.-Y. Meng. 'Semimodularity and self diagnostic asynchronous control circuits,' In Advanced Research in VLSI, Proc. of the 1991 Univ. of CA/Santa Cruz Conference. The MIT Press, Cambridge, MA, 1991
  3. P. Day and J. Viv. Woods, 'Investigation into Micropipeline Latch Design Styles,' to be published in IEEE Trans. on VLSI circuits, June 1995 https://doi.org/10.1109/92.386226
  4. J. A. Brzozowski and C.-J. Seger. 'A unified framework for race analysis of asynchronous network,' Journal of the ACM, 36(1), pp.20-45, Jan. 1989 https://doi.org/10.1145/58562.59301
  5. P. A. Beerel and T. H.-Y. Meng. 'Semimodularity and testability of speed-independent circuits,' Integration, the VLSI journal, 13(3), pp.301-322, Sep. 1992
  6. Gerald R. Carson and Gaetano Borriello, 'A testable CMOS asynchronous counter,' IEEE Journal of Solid-State Circuits, 25(40), August 1990 https://doi.org/10.1109/4.58287
  7. A. Martin and Pieter J. Hazewindus, 'Testing delay-insensitive circuits,' Proc. of the 1991 UC Santa Cruz Conf. pp.118-132, The MIT Press, Cambridge, MA, 1991
  8. P. J. Hazenwindus, 'Testing Delay-Insensitive Circuits,' Ph.D thesis, Caltech, 1992
  9. Marly Roncken, Emile Aarts and Wim Verhaegh, 'Optimal Scan for Pipelined Testing : An Asynchronous Foundation,' Philips Research Laboratories, International Test Conference, IEEE 1996 https://doi.org/10.1109/TEST.1996.556964
  10. Chin-Long Wey, Ming-Der Shieh, D. Fisher, 'ASCLScan : ascan design for asynchronous sequential logic circuits,' Proc. of IEEE International Conference on Computer Aided Design, pp. 159-162, 1993 https://doi.org/10.1109/ICCD.1993.393388
  11. D. Rana, S. P. Levitan, D. A. Carlson, and C. E. Hutchinson, 'A testable asynchronous systolic array implementation of an IIR filter,' Proc. of IEEE CICC, pp.90-93, May, 1986
  12. I. E. Sutherland, 'Micropipelines,' Communications of the ACM, Vol. 32, no. 6, pp. 720-738, June 1989 https://doi.org/10.1145/63526.63532
  13. O. A. Petlin, C. Farnsworth, S. B. Furber, 'Built-in self test design of an asynchronous block sorter,' Department of Computer Science, The University, Manchester. 1997
  14. O. Petlin, S. Furber, 'Scan testing of micropipelines,' Proc. of IEEE VLSI Test Symposium, pp. 296-301, 1995 https://doi.org/10.1109/VTEST.1995.512652
  15. A. Khoche, E. Brunvand, 'Testing micropipelines,' Proc. of International Symposium on Advanced Research in Asynchronous Circuits and System, pp.239-246, 1994 https://doi.org/10.1109/ASYNC.1994.656316
  16. Volker Schober, Thomas Kiel, 'An asynchronous scan path concept for micropipelines using the bundled data convention,' Proc. of IEEE International Test Conference, pp. 225-231, 1996 https://doi.org/10.1109/TEST.1996.556965
  17. S. Pagey, G. Venkatesh, S. Sherlekar, 'Issues in fault modelling and testing of micropipelines,' Proc. of IEEE Asian Test Symposium, pp. 132-138, 1992 https://doi.org/10.1109/ATS.1992.224446
  18. O. A. Petlin, S. B. Furber, 'Scan testing of asynchronous sequential circuits,' Proc. of Great Lakes Symposium on VLSI, pp. 224-229, 1995 https://doi.org/10.1109/GLSV.1995.516057
  19. O. A. Petlin, S. B. Furber, 'Built-in self-testing of micropipelines,' Department of Computer Science, University of Manchester, 1996
  20. S. Devadas and K. Kuetzer, 'Synthesis and optimization procedures for robustly delay-fault testable logic circuilts,' Proc. of IEEE Design Automation Conference, pp. 221-227. 1990 https://doi.org/10.1109/DAC.1990.114858
  21. S. Devadas and K. Keutzer, 'Design of integrated circuits fully testable for delay faults and multifaults,' Proc. of IEEE International Test Conference, pp.284-293, 1990 https://doi.org/10.1109/TEST.1990.114034
  22. J. A. Waicukauski, E. Lindbloom, B. Rosen and V. Iyengar, 'Transition fault simulation,' IEEE Design and Test, pp. 32-38, Apr. 1987
  23. T. Hayashi, K. Hatayama, S. Ishiyama, and M. Takakura, 'Two test generation methods for sequential circuits,' Proc. of IEEE International Symposium Circuits and Systems, pp.1942-1945, 1989 https://doi.org/10.1109/ISCAS.1989.100750
  24. S. Kang, B. Underwood and W. Law, 'Path Delay Fault simultation for a Standard Scan Design Methodology,' Proc. of IEEE International Conference on Circuits Design, 1994 https://doi.org/10.1109/ICCD.1994.331926
  25. B. Underwood, W.-O. Law, S. Kang, H. Konuk, 'Fastpath: A Path-Delay Test Generator for Standard Scan Designs,' Proc. of IEEE International Test Conference, pp. 154-163, 1994 https://doi.org/10.1109/TEST.1994.527946