대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

CMOS 이미지 센서의 영상 개선을 위한 실시간 전처리 프로세서의 설계

Design of Real-Time PreProcessor for Image Enhancement of CMOS Image Sensor

  • 정윤호 (延世大學校 電氣 電子工學科 情報通信用 ASIC設計 硏究室) ;
  • 이준환 (延世大學校 電氣 電子工學科 情報通信用 ASIC設計 硏究室) ;
  • 김재석 (延世大學校 電氣 電子工學科 情報通信用 ASIC設計 硏究室) ;
  • 임원배 (延世大學校 電氣 電子工學科 超解像度 映像處理 硏究室) ;
  • 허봉수 (延世大學校 電氣 電子工學科 超解像度 映像處理 硏究室) ;
  • 강문기 (延世大學校 電氣 電子工學科 超解像度 映像處理 硏究室)
  • Jung, Yun-Ho (Dept. fo Electrical and Electronic Engineering, Communication ASIC Design Lab., Yonsei Univ.) ;
  • Lee, Joon-Hwan (Dept. fo Electrical and Electronic Engineering, Communication ASIC Design Lab., Yonsei Univ.) ;
  • Kim, Jae-Seok (Dept. fo Electrical and Electronic Engineering, Communication ASIC Design Lab., Yonsei Univ.) ;
  • Lim, Won-Bae (Dept. of Electrical and Electronic Engineering Superresolution Image Processing Lab., Yonsei Univ.) ;
  • Hur, Bong-Soo (Dept. of Electrical and Electronic Engineering Superresolution Image Processing Lab., Yonsei Univ.) ;
  • Kang, Moon-Gi (Dept. of Electrical and Electronic Engineering Superresolution Image Processing Lab., Yonsei Univ.)
  • 발행 : 2001.08.01
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초록

본 논문은 CMOS 이미지 센서에서 획득한 영상의 품질을 개선하기 위한 실시간 전처리 프로세서의 설계를 제시한다. CMOS 이미지 센서는 기존 IC와의 통합, 저전력소모, 저가격화등의 다양한 이점을 갖지만, 기존의 CCD 소자로부터 획득한 영상에 비해 열등한 품질의 영상을 제공하는 단점이 있다. CMOS 이미지 센서의 이러한 물리적 한계를 극복하기 위해 본 논문에서 제안하는 전처리 프로세서에는 색상 보간, 색상 보정, 감마 보정, 자동 노출 조정 등의 기본적인 전처리 알고리즘 외에 공간 가변적 대비 향상 알고리즘이 포함되었다. 여기에서 제안하는 전처리 프로세서는 이러한 알고리즘을 효율적으로 구현하기 위한 하드웨어 구조를 가지며, VHDL 언어를 이용하여 설계 및 검증되었다. 설계된 전처리 프로세서는 합성 결과 약 19K의 논리 게이트를 포함하였으며, 이는 저가격의 PC 카메라 구현에 적합하다. 제안된 전처리 프로세서의 실시간 동작 여부를 검증하기 위해 설계된 전처리 프로세서는 Altera사의 Flex EPF10KGC503-3 FPGA 칩으로 구현되었으며, 성공적으로 동작함을 확인하였다.

This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on Altera Flex EPF10KGC503-3 FPGA chip in real-time mode, and performed successfully.

키워드

참고문헌

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