Journal of KIISE:Information Networking (한국정보과학회논문지:정보통신)

Korean Institute of Information Scientists and Engineers (한국정보과학회)
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Performance Evaluation of a Multistage Interconnection Network with Output-Buffered ${\alpha}{\times}{\alpha}$ Switches

출력 버퍼형${\alpha}{\times}{\alpha}$스위치로 구성된 다단 연결망의 성능 분석

  • 신태지 (울산대학교 전기전자정보시스템공학부) ;
  • 양명국 (울산대학교 전기전자정보시스템공학부)
  • Published : 2002.12.01
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Abstract

In this paper, a performance evaluation model of the Multistage Interconnection Network(MIN) with the multiple-buffered crossbar switches is Proposed and examined. Buffered switch technique is well known to solve the data collision problem of the MIN. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. The performance of the multiple-buffered${\alpha}{\times}{\alpha}$ crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes, Two important parameters of the network performance, throughput and delay, are then evaluated, To validate the proposed analysis model, the simulation is carried out on a Baseline network that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

본 논문에서는, ${\alpha}{\times}{\alpha}$ 출력 버퍼 스위치로 구성된 다단 연결 망(Multistage Interconnection Network, MIN)의 성능 예측 모형을 제안하고, 스위치에 장착된 버퍼의 개수 증가에 따른 성능 향상 추이를 분석하였다. Buffered 스위치 기법은 다단 연결 망 내부의 데이타 충들 문제를 효과적으로 해결할 수 있는 방법으로 널리 알려져 있다. 제안한 성능 예측 모형은 먼저 네트웍 내부 임의 스위치 입력 단에 유입되는 데이타 패킷이 스위치 내부에서 전공되는 유형을 확률적으로 분석하여 수립되었다. 제안한 모형은 스위치에 장착된 버퍼의 개수와 무관하게 출력 버퍼를 장착한 ${\alpha}{\times}{\alpha}$스위치의 성능, 즉 네트웍 성능 평가의 두 가지 주요 요소인 네트웍 정상상태 처리율(Normalized Throughput, NT)과 네트웍 지연시간(Network Delay)의 예측이 가능하고, 나아가서 이들로 구성된 모든 종류의 다단 연결 망 성 분석에 적용이 용이하다. 제안한 수학적 성능 분석 연구의 실효성 검증을 위하여 병행된 시뮬레이션 결과는 상호 미세한 오차 범위 내에서 모형의 예측 데이타와 일치하는 곁과를 보며 분석 모형의 타당성을 입증하였다. 또한, 분석 결과 스위치 내부에 많은 버퍼를 장착할수록 정상상태 처리율의 증가율은 감소하고, 네트웍 지연시간은 증가하는 것으로 나타났다.

Keywords

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