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다결정 다공성 실리콘의 전계방출 특성

Electron Emission From Porous Poly-Silicon Nano-Device for Flat Panel Display

  • 이주원 (한국과학기술연구원) ;
  • 김훈 (한국과학기술연구원) ;
  • 이윤희 (고려대학교 물리학과) ;
  • 장진 (경희대학교 물리학과) ;
  • 주병권 (한국과학기술연구원)
  • 발행 : 2003.04.01

초록

This paper reports the optimum structure of the vacuum packaged Porous poly-silicon Nano-Structured (PNS) emitter. The PNS layer was obtained by electrochemical etching process into polycrystalline silicon layer in a process controlled to anodizing condition. Current-voltage studies were carried out to optimize process condition of electron emission properties as a function of anodizing condition and top electrode thickness. Also, we measured in advance the electron emission properties as a function of substrate temperature because the vacuum packaged process was performed under the condition of high temperature ambient (430$^{\circ}C$). Auger Electron Spectrometer (AES) studies shows that Au as a top-electrode was diffused to PNS layer during temperature experiments. Thus, we optimized the thickness of top-electrode in order to make the vacuum package PNS emitter. As a result, the vacuum Packaged PNS emitter was successfully emitted by optimizing process.

키워드

참고문헌

  1. 전기전자재료학회논문지 v.11 no.1 FED 기술 및 연구 개발 동향 이윤희;오명환;주병권;이남양
  2. 전기전자재료학회논문지 v.11 no.7 몰리브덴 팁 전계 방출 소자의 제조 및 다이아몬드 상 카본의 코팅 효과 이윤희;정재훈;오명환;김훈;주병권;이상조;차균현
  3. 99년도 춘계학술대회논문집 Field Emission Display 의 고진공 실장에 관한 연구 장진;주병권;이덕중;오명환
  4. proceed. SID 00 Matrix flat panel application of ballistic electron surface-emitting display T. Komoda;Y. Honda;T. Hatai;Y. Watabe;T. Ichihara;K. Aizawa;Y. Kondo;N. Koshida
  5. proceed. SID'02 Optimization and characterization of porous poly-silicon emitter H. Kim;J. W. Lee
  6. proceed. IMID'02 Electrical properties of the Porous polycrystalline silicon Nano-Structure as a cold cathode field emitter J. W. Lee;H. Kim
  7. J. Vac. Sci. Tech. B v.17 no.3 Mechanism of efficient and stable surface-emitting cold cathode based on porous polycrystalline siliconfilms T. Komoda;X. Sheng;N. Koshida https://doi.org/10.1116/1.590696
  8. Metallization: Theory and Practice for VLSI and ULSI Shyam P. Murarka