분산산술연산방식을 이용한 MPEG-1 오디오 계층 3 합성필터의 FPGA 군현

An FPGA Implementation of the Synthesis Filter for MPEG-1 Audio Layer III by a Distributed Arithmetic Lookup Table

  • 발행 : 2004.11.01

초록

반도체 기술과 멀티미디어 통신기술이 발달하면서 고품위 영상과 다중 채널의 오디오에 관심을 갖게 되었다. MPEG 오디오 계층 3 디코더는 표준안에 기반을 둔 프로세서로써 기존에 많이 구현되어 있다. MPBG-1오디오 계층3 디코더의 합성필터는 디코더 전체에서 가장 많은 연산을 필요로 하기 때문에 고속 프로세서를 설계하기 위해서는 연산량을 줄일 수 있는 새로운 방식의 합성필터를 필요로 한다. 따라서 본 논문에서는 MPEG-1 오디오 계층 3의 핵심부분인 합성필터 부분을 DALUT (distributed arithmetic look-up table)방식을 이용하여 FPGA (Field Programmable Gate Array)에 구현하였다. 고속 필터를 설계하기 위해서 승산기 대신에 DALUT방식을 사용하였고, 파이프라인 구조를 사용하였으며, 데이터를 코사인 함수와 곱셈한 결과를 테이블로 만듦으로써 곱셈기를 제거하여 30%의 성능향상을 얻었다. 본 논문에서의 하드웨어 설계는 모두 VHDL (VHSIC Hardware Description Language)로 기술하였다. VHDL 시뮬레이션은 ALDEC사의 Active-HDL 6.1과 Model-sim 및 합성은 Synplify Pro 7.2v을 사용하였다. 대상 라이브러리는 XILINX사의 XC4010E, XC4020BX, XC4052 XL, P&R 툴은 XACT Ml.4를 사용하여 구현하였다. 구현된 프로세서는 20MHz∼70MHz사이에서 동작한다.

As the technologies of semiconductor and multimedia communication have been improved. the high-quality video and the multi-channel audio have been highlighted. MPEG Audio Layer 3 decoder has been implemented as a Processor using a standard. Since the synthesis filter of MPEG-1 Audio Layer 3 decoder requires the most outstanding operation in the entire decoder. the synthesis filter that can reduce the amount of operation is needed for the design of the high-speed processor. Therefore, in this paper, the synthesis filter. the most important part of MPEG Audio, is materialized in FPGA using the method of DAULT (distributed arithemetic look-up table). For the design of high-speed synthesis filter, the DAULT method is used instead of a multiplier and a Pipeline structure is used. The Performance improvement by 30% is obtained by additionally making the result of multiplication of data with cosine function into the table. All hardware design of this Paper are described using VHDL (VHIC Hardware Description Language) Active-HDL 6.1 of ALDEC is used for VHDL simulation and Synplify Pro 7.2V is used for Model-sim and synthesis. The corresponding library is materialized by XC4013E and XC4020EX. XC4052XL of XILINX and XACT M1.4 is used for P&R tool. The materialized processor operates from 20MHz to 70MHz.

키워드

참고문헌

  1. Davis Pan, 'A Tutorial on MPEG/Audio Compression' Motorola Inc
  2. KEN C. POHLMAN, PRINCIPLES OF DIGITAL AUDIO 3rd Edition, (McGraw-Hili, 1997), 354-415
  3. J. Princen, A.Johnson, A. Bradley, 'Subband/Transform Coding Using Filter Bank Designs Based on Time Domain Aliasing Cancellation', Proc, of the ICASSP, pp. 2161-2164, 198
  4. The Sorer, Kh. Brandenburg, 'The use of multi rate filter banks for coding of high quality digital audio'6th European Signal Processing Conference, Amsterdam, 1, pages 211214,June 1992
  5. Ted painter, Andreas Spanias, 'A Review of Algorithms for Perceptual Coding of Digital Audio Signals' Department of Electrical Engineering, Telecommunications Research Center Arizona State University
  6. 'The Role of Distributed Arithmetic in FPGA based Signal Processing' www.xilinx.com
  7. P.P. VAlDYANATHAN, MULTIRATE SYSTEMS AND FILTER BANKS, (Prentice Hall Englewood Clieffs, 1993)
  8. ALEXANDER D.POULARIKAS, 'The Transforms and Applications Hand Book' CRC and IEEE PRESS, 1996
  9. ISO/IEC JTC1/SC29/WG11 MPEG, International Standard IS 13818-3 (Second Edition) 'Information Technology-- Generic Coding of Moving Pictures and Associated Audio, Part 3: Audio', 1997
  10. Vijay K. Madisetti VLSI digital signal processors An Introduction to Rapid Prototyping and Design Synthesis' IEEE PRESS