Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Low-Cost Elliptic Curve Cryptography Processor Based On Multi-Segment Multiplication

멀티 세그먼트 곱셈 기반 저비용 타원곡선 암호 프로세서

  • LEE Dong-Ho (School of Electrical Engineering and Computer Science, Kyungpook National University)
  • 이동호 (경북대학교 전자전기컴퓨터학부)
  • Published : 2005.08.01
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Abstract

In this paper, we propose an efficient $GF(2^m)$ multi-segment multiplier architecture and study its application to elliptic curve cryptography processors. The multi-segment based ECC datapath has a very small combinational multiplier to compute partial products, most of its internal data buses are word-sized, and it has only a single m bit multiplexer and a single m bit register. Hence, the resource requirements of the proposed ECC datapath can be minimized as the segment number increases and word-size is decreased. Hence, as compared to the ECC processor based on digit-serial multiplication, the proposed ECC datapath is more efficient in resource usage. The resource requirement of ECC Processor implementation depends not only on the number of basic hardware components but also on the complexity of interconnection among them. To show the realistic area efficiency of proposed ECC processors, we implemented both the ECC processors based on the proposed multi-segment multiplication and digit serial multiplication and compared their FPGA resource usages. The experimental results show that the Proposed multi-segment multiplication method allows to implement ECC coprocessors, requiring about half of FPGA resources as compared to digit serial multiplication.

본 논문에서는 효율적인 $GF(2^m)$ 멀티 세그먼트 곱셈 연산 구조를 제안하고 제안된 구조의 타원곡선 암호 프로세서 설계 응용을 연구한다. 제안된 멀티 세그먼트 곱셈 연산 구조는 유한체 크기 m에 비하여 아주 작은 워드 조합 곱셈기를 이용하여 부분곱을 계산하고 거의 모든 내부 버스는 워드 크기이며 m 비트 멀티플렉서와 m 비트 레지스터를 하나만 사용한다. 따라서 조합 곱셈기의 워드 크기 w를 줄이고 세그먼트 수 k를 크게 하여 전체 데이터패스 자원 사용량이 최소화할 수 있다. 제안된 곱셈기는 디지트 시리얼 곱셈기로 구현된 ECC 프로세서와 비교할 때 이론적으로 자원 효율성이 우수하다 암호 프로세서의 자원 사용량은 구현에 필요한 기본 하드웨어 요소 수뿐만 아니라 구성 요소들의 배치와 연결 상태에도 의존한다. 제안된 프로세서의 실질적인 자원사용량을 디지트 시리얼 곱셈기 기반 암호 프로세서와 비교하기 위하여 두 종류의 프로세서를 FPGA 상에 구현하였다. 실험 결과로 제안된 멀티 세그먼트 곱셈기 기반 EU 프로세서는 유사한 성능을 가지는 디지트 시리얼 곱셈기 기반 EU 프로세서보다 자원 사용면에서 2배 정도 우수함을 보였다.

Keywords

References

  1. D. Hankerson, J. L. Hernandez, and A. Menezes, 'Software implementation of elliptic curve cryptography over binary fields,' Cryptographic Hardware and Embedded Systems(CHES 2000), LNCS 1965, Springer, pp. 2-24, Worcester, MA, USA, August 2000
  2. M. Brown, D. Hankerson, J. Lopez, and A. Menezes, 'Software implementation of the NIST elliptic curves over prime fields,' CT-RSA 2001, LNCS 2020, Springer, pp. 250-265, 2001
  3. M. Rosing, Implementing Elliptic Curve Cryptography, Manning Publications Co., 1999
  4. G. B. Agnew, R. C. Mullin, and S. A. Vanstone, 'An implementation of elliptic curve cryptosystems over $F_{2}^{155}$,' IEEE Journal on Selected Areas in Communications, Vol. 11, no. 5, pp. 804-813, June 1993 https://doi.org/10.1109/49.223883
  5. J. Lopez and R. Dahab, 'Fast multiplication on elliptic curves over $GF(2^m)$ without precomputation,' Cryptographic Hardware and Embedded Systems(CHES '99), LNCS 1717, Springer, pp. 316-327, Worcester, MA, USA, August 1999 https://doi.org/10.1007/3-540-48059-5_27
  6. L. Song and K. K. Parhi, 'Low-energy digit-serial/parallel finite field multipliers,' Journal of VLSI Signal Processing Systems, Vol. 2, no. 22, pp. 1-17, August 1997
  7. G. Orlando and C. Paar, 'A high-performance reconfigurable elliptic curve processor for $GF(2^m)$,' Cryptographic Hardware and Embedded Systems(CHES 2000), LNCS 1965, Springer, pp. 41-56, Worcester, MA, USA, August 2000
  8. E. Savas, A. F. Tenca, and C. K. Koc, 'A scalable and unified multiplier architecture for finite fields GF(p) and $GF(2^m)$,' Cryptographic Hardware and Embedded Systems(CHES 2000), LNCS 1965, Springer, pp. 277-292, Worcester, MA, USA, August 2000
  9. M. Ernst, M, Jung, F. Madlener, S. Huss, and R. Bluemel, 'A reconfigurable system on chip implementation for elliptic curve cryptography over $GF(2^m)$,' Cryptographic Hardware and Embedded Systems(CHES 2002), LNCS 2523, Springer, pp. 382-399, Worcester, MA, USA, August 2002
  10. H. Wu, 'Low complexity bit parallel finite field arithmetic using polynomial basis,' Cryptographic Hardware and Embedded Systems(CHES '99), LNCS 1717, Springer, pp. 280-291, Worcester, MA, U.S.A, August 1999 https://doi.org/10.1007/3-540-48059-5_24
  11. Quartus-II S/W On Line Manual, Altera Corp, http://www.altera.com/product/software/pld/q2/qts-index.html
  12. K. H. Leung, K. W. Ma, W. K. Wong, and P. H. W. Leong, 'FPGA implementation of a microcoded elliptic curve cryptography processor,' 2000 IEEE Symposium on Field Programmable Custom Computing Machines, pp. 68-76, Napa Valley, CA, U.S.A, April 17-19, 2000 https://doi.org/10.1109/FPGA.2000.903394