ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Voltage-Mode 1.5 Gbps Interface Circuits for Chip-to-Chip Communication

  • Lee, Kwang-Jin (Department of Electronics Engineering, Korea University) ;
  • Kim, Tae-Hyoung (Division of SRAM Design, Samsung Electronics) ;
  • Cho, Uk-Rae (Division of SRAM Design, Samsung Electronics) ;
  • Byun, Hyun-Geun (Division of SRAM Design, Samsung Electronics) ;
  • Kim, Su-Ki (Department of Electronics Engineering, Korea University)
  • Received : 2004.08.17
  • Published : 2005.02.28
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Abstract

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

Keywords

References

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