CPLD 소자를 사용한 DDS 방식의 고속 주파수 호핑용 디지털 주파수 합성기의 설계

Design of the Digital Frequency Synthesizer for High Speed Frequency Hopping by the DDS Method using CPLD

  • 김기래 (신라대학교 공과대학 전자공학과) ;
  • 최영규 (신라대학교 공과대학 전자공학과)
  • 발행 : 2005.04.01

초록

주파수 합성기로서 통신시스템에 많이 사용되어온 PLL 방식은 여러 장점을 갖고 있지만, 위상잡음 특성이 나쁘고 주파수 도약 시간이 긴 단점을 갖기 때문에 최근의 고속(l$mu$s이하)으로 주파수 호핑(Frequency Hopping)을 요구하는 차세대 이동 통신 시스템에서는 사용이 불가능하다. 본 연구는 차세대 이동통신 시스템에서 1600 hops/s 속도로 600개 이상의 랜덤한 주파수를 발생하는 주파수합성기를 CPLD를 사용하여 DDS (Direct Digital Synthesis) 방식으로 설계하였다.

The PLL synthesizer is used in communication system until now because it have several merits, such as broad bandwidth, high accuracy and stability of frequency But it is difficult to use in the third generation mobile communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed the frequency synthesizer that generate frequencies randomly at a high speed using the DDS technology.

키워드

참고문헌

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