대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

AMBA 기반 SoC 테스트를 위한 접근 메커니즘 설계

Design of Test Access Mechanism for AMBA based SoC

  • 민필재 (한양대학교 컴퓨터공학과) ;
  • 송재훈 (한양대학교 컴퓨터공학과) ;
  • 이현빈 (한양대학교 컴퓨터공학과) ;
  • 박성주 (한양대학교 전자컴퓨터공학부)
  • Min, Pil-Jae (Department of Computer Science & Engineering, Hanyang University) ;
  • Song, Jae-Hoon (Department of Computer Science & Engineering, Hanyang University) ;
  • Yi, Hyun-Bean (Department of Computer Science & Engineering, Hanyang University) ;
  • Park, Sung-Ju (Department of Electrical Engineering Computer Science, Hanyang University)
  • 발행 : 2006.10.25
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

Advanced Microcontroller Bus Architecture (AMBA) 기반 System-on-Chip (SoC)에서는 기능적 테스트를 위해 ARM사의 Test Interface Controller (TIC)를 사용한다. 따라서 구조적 스캔 테스트 패턴도 TIC와 AMBA 버스를 통해 인가하면서 스캔입력과 출력을 동시에 수행할 수 없다는 단점이 있다. 본 논문에서는 ARM 코어를 사용하는 SoC 테스트를 위한 AMBA based Test Access Mechanism (ATAM)을 제안한다. 기존 TIC와의 호환성을 유지하고 스캔 입력과 출력을 동시에 할 수 있으므로 고가의 Automatic Test Equipment (ATE)를 통한 테스트 시간을 대폭 절감할 수 있다.

Test Interface Controller (TIC) provided by ARM Ltd. is widely used for functional testing of System-on-Chip (SoC) adopting Advanced Microcontroller Bus Architecture (AMBA) bus system. Accordingly, this architecture has a deficiency of not being able to concurrently shifting in and out the structural scan test patterns through the TIC and AMBA bus. This paper introduces a new AMBA based Test Access Mechanism (ATAM) for speedy testing of SoCs embedding ARM cores. While preserving the compatability with the ARM TIC, since scan in and out operations can be performed simultaneously, test application time through the expensive Automatic Test Equipment (ATE) can be drastically reduced.

키워드

참고문헌

  1. Y. Zorian, E. J. Marinissen and S. Dey, 'Testing Embedded-core based System Chips,' In Proceedings IEEE International Test Conference, pp. 130- 143, Oct. 1998. https://doi.org/10.1109/TEST.1998.743146
  2. ARM IHI 0011A, 'AMBA Specification (Rev 2.0)'. May 1999
  3. M. Abramovici, M. Breuer, and A. Friedman, 'Digital Systems Testing and Testable Design,' ？IEEE Press, New York, 1990
  4. C. Feige et al, 'Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach,' Journal of Electronic Testing, Volume 14, pp. 125-131, July 1998 https://doi.org/10.1023/A:1008313726031
  5. C. Lin and H. Liang, 'Bus-Oriented DFT Design for Embedded Cores,' IEEE Asia-Pacific Conference, Volume 1, pp. 561-563, Dec. 2004 https://doi.org/10.1109/APCCAS.2004.1412823
  6. P. Harrod, 'Testing Reusable IP - A Case Study,' In Proceedings of IEEE International Test Conference, pp. 493-498, Sep 1999 https://doi.org/10.1109/TEST.1999.805772
  7. J. Aerts and E.J. Marinissen, 'Scan Chain Design for Test Time Reduction in Core-Based ICs,' Proc. Int'l Test Conf., pp. 448-457, 1998 https://doi.org/10.1109/TEST.1998.743185
  8. E. J. Marinissen et al, 'A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores,'In Proceedings IEEE International Test Conference, Oct. 1998 https://doi.org/10.1109/TEST.1998.743166
  9. I. Hamzaoglu and J. H. Patel, 'Reducing Test Application Time for Full-Scan Embedded Cores,' Proc. 29th Int'l Symp, Fault-Tolerant Computing (FTCS 99), Digest of Papers, IEEE CS Press, Los Alamitos, Calif., pp. 260-267, 1999 https://doi.org/10.1109/FTCS.1999.781060
  10. Advanced RISC Machines, 'AHB Example AMBA System Technical Reference Manual,' ARM DDI 0170A, Aug. 1999
  11. Advanced RISC Machines, 'ARM PrimeCell External Bus Interface (PL220),' ARM DDI 0249B, Dec. 2002
  12. ALTERA, 'Excalibur Devices Hardware Reference Manual,' Version 3.1, Nov. 2002
  13. Atmel Corporation, 'AT91 ARM Thumb Microcontrollers,' AT91R40807, Jan. 2002
  14. J. Gaisler and E. Catovic, 'Gaisler Research IP Core's Manual,' version 1.0.1, Jun. 2005