Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Interconnect Delay Fault Test in Boards and SoCs with Multiple System Clocks

다중 시스템 클럭으로 동작하는 보드 및 SoC의 연결선 지연 고장 테스트

  • Lee Hyunbean (Dept. of Computer Science & Engineering, Hanyang Univ.) ;
  • Kim Younghun (Dept. of Computer Science & Engineering, Hanyang Univ.) ;
  • Park Sungju (Dept. of Electronical Engineering Computer Science, Hanyang Univ.) ;
  • Park Changwon (Korea Electronics Technology Institutes(KETI) Intelligent IT System Research Center)
  • 이현빈 (한양대학교 컴퓨터공학과) ;
  • 김영훈 (한양대학교 컴퓨터공학과) ;
  • 박성주 (한양대학교 전자컴퓨터공학과) ;
  • 박창원 (전자부품연구원 지능형정보시스템 연구센터)
  • Published : 2006.01.01
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Abstract

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller is simple in terms of test procedure and is small in terms of area overhead.

본 논문은, IEEE 1149.1 및 IEEE P1500 기반의 보드 및 SoC의 연결선 지연 고장 테스트를 위한 회로 및 테스트 방법을 제안한다. IDFT 모드 시, 출력 셀의 Update와 입력 셀의 Capture가 한 시스템 클럭 간격 내에 이루어지도록 하는 시스템 클럭 상승 모서리 발생기를 구현한다. 이 회로를 이용함으로써, 단일 시스템 클럭 뿐만 아니라 다중 시스템 클럭을 사용하는 보드 및 SoC의 여러 연결선의 지연 고장 테스트를 쉽게 할 수 있다. 기존의 방식에 비해 면적 오버헤드가 적고 경계 셀 및 TAP의 수정이 필요 없으며, 테스트 절차도 간단하다는 장점을 가진다.

Keywords

References

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