Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A New TWA-Based Efficient Signal Integrity Verification Technique for Complicated Multi-Layer RLC Interconnect Lines

복잡한 다층 RLC 배선구조에서의 TWA를 기반으로 한 효율적인 시그널 인테그러티 검증

  • Jo Chan-Min (Hanyang University, Dept. of Electrical and Computer Engineering) ;
  • Eo Yung-Seon (Hanyang University, Dept. of Electrical and Computer Engineering)
  • 조찬민 (한양대학교 전자컴퓨터공학) ;
  • 어영선 (한양대학교 전자컴퓨터공학)
  • Published : 2006.07.01
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Abstract

A new TWA(Traveling-wave-based Waveform Approximation)-based signal integrity verification method for practical interconnect layout structures which are composed of non-uniform RLC lines with various discontinuities is presented. Transforming the non-uniform lines into virtual uniform lines, signal integrity of the practical layout structures can be very efficiently estimated by using the TWA-technique. It is shown that the proposed technique can estimate the signal integrity much more efficiently than generic SPICE circuit model with 5% timing error and 10% crosstalk error.

본 논문에서는 불규칙하고 복잡한 다층(multi-layer) RLC 배선에 대하여 TWA(Traveling-wave-based Waveform Approximation)을 기반으로 한 새로운 시그널 인테그러티 검증에 대한 방법을 제시한다. 실제 레이아웃 구조의 불규칙한 배선을 가상 직선 배선으로 변환하고 이를 TWA 기법을 사용하여 효율적으로 검증하였다. 여기서 제안된 방법은 3차원 구조에 대한 회로 모델을 사용한 일반적인 SPICE 시뮬레이션에 비하여 계산시간을 현저하게 단축시킬 수 있으며, 타이밍의 경우 5% 이내에서, 크로스톡의 경우 10% 이내에서 정확하다는 것을 보인다.

Keywords

References

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