Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Stochastic Glitch Estimation and Path Balancing for Statistical Optimization

통계적 최적화를 위한 확률적 글리치 예측 및 경로 균등화 방법

  • Shin Ho-Soon (Semicondoctor Business SAMSUNG ELECTRONICS CO., LTD.) ;
  • Kim Ju-Ho (Department of Computer Science and Eng., Sogan University) ;
  • Lee Hyung-Woo (Semicondoctor Business SAMSUNG ELECTRONICS CO., LTD.)
  • 신호순 ((주) 삼성전자 반도체총괄) ;
  • 김주호 (서강대학교 컴퓨터학과) ;
  • 이형우 ((주) 삼성전자 반도체총괄)
  • Published : 2006.08.01
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Abstract

In the paper, we propose a new method for power optimization that uses path balancing based on stochastic estimation of glitch in Statistical Static Timing Analysis (SSTA). The proposed method estimates the probability of glitch occurrence using tightness probability of each node in timing graph. In addition, we propose efficient gate sizing technique for glitch reduction using accurate calculation of sizing effect in delay considering probability of glitch occurrence. The efficiency of proposed method has been verified on ISCAS85 benchmark circuits with $0.16{\mu}m$ model parameters. Experimental results show up to 8.6% of accuracy improvement in glitch estimation and 9.5% of optimization improvement.

이 논문에서는 공정 변이의 고려를 위한 통계적 시간 분석(statistical timing analysis)에서 전력감소를 고려한 회로의 최적화를 위해 글리치 및 지연시간의 확률적 모델 및 연산을 이용하여 각 경로 및 경로상의 게이트의 민감도(sensitivity)를 계산하고 이를 이용한 사이징(sizing)을 통해 회로의 지연시간의 증가 없이 글리치를 감소하는 방법을 제시한다. 제안된 알고리즘은 통계적 시간 분석에 근거한 회로의 전후방 탐색을 이용하여 공정 변수를 고려한 확률적 글리치 발생률을 예측한다. 또한 글리치 발생률을 고려한 게이트의 선택 및 사이징 가능한 지연시간의 최적화된 계산을 통해 효율적인 게이트 사이징 기법과 글리치 감소를 위한 경로균등화 방법을 제시한다. 제안된 알고리즘의 효율성은 $0.16{\mu}m$ 모델 파라미터를 이용하여 ISCAS85 벤치마크 회로에 대한 실험을 통해 검증되었다. 실험 결과를 통해 제안된 알고리즘은 글리치 예측에 있어 8.6%의 정확도의 개선을 보였고, 경로균등화에 의한 최적화에 있어 9.5%의 개선을 보였다.

Keywords

References

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