Journal of Electrical Engineering and Technology

  • 제1권3호
  • /
  • Pages.396-405
  • /
  • 2006
  • /
  • 1975-0102(pISSN)
  • /
  • 2093-7423(eISSN)
대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지
DOI QR코드

DOI QR Code

3-Dimensional Numerical Analysis of Deep Depletion Buried Channel MOSFETs and CCDs

  • Kim Man-Ho (School of Electronical Engineering, University of Ulsan)
  • 발행 : 2006.09.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

The visual analysis of buried channel (Be) devices such as buried channel MOSFETs and CCDs (Charge Coupled Devices) is investigated to give better understanding and insight for their electrical behaviours using a 3-dimensional (3-D) numerical simulation. This paper clearly demonstrates the capability of the numerical simulation of 'EVEREST' for characterising the analysis of a depletion mode MOSFET and BC CCD, which is a simulation software package of the semiconductor device. The inverse threshold and punch-through voltages obtained from the simulations showed an excellent agreement with those from the measurement involving errors of within approximately 1.8% and 6%, respectively, leading to the channel implanted doping profile of only approximately $4{\sim}5%$ error. For simulation of a buried channel CCD an advanced adaptive discretising technique was used to provide more accurate analysis for the potential barrier height between two channels and depletion depth of a deep depletion CCD, thereby reducing the CPU running time and computer storage requirements. The simulated result for the depletion depth also showed good agreement with the measurement. Thus, the results obtained from this simulation can be employed as the input data of a circuit simulator.

키워드

참고문헌

  1. R. W. Knepper, 'Dynamic depletion mode: An E/D MOSFET circuit for improved performance' IEEE J. Solid-State Circuits, vol. SC-13, pp. 542-548, Oct. 1978
  2. M. H. Kim, 'Open electrode CCD UV/XUV sensitive detectors for astronomy' Internal Report, University of Leicester, UK, 1993
  3. G. W. Taylor, P. K. Chatterjee, and H. H. Chao, 'A device model for buried - channel CCD's and MOSFET's for Gaussian impurity profiles' IEEE Trans. Electron Devices, vol. ED-27, pp. 199-208, Jan. 1980
  4. IEEE Trans. Electron Devices (Special Issue on SOS Technology and Nonvolatie Memory Technology), vol. ED-25, no. 8, 1978
  5. S. Karmalkar and K. N. Bhat, 'The correct equivalent box representation for the buried layer of the BC MOSFETs in terms of the implantation parameters' IEEE Electron Devices Lett., vol. EDL-8, pp. 457-459, Oct. 1985
  6. A. B. Bhattacharya et al. 'On-line extraction of model parameters of a long buried-channel MOSEFT' IEEE Trans. Electron Devices, vol. ED-32, pp. 545 - 550, Mar. 1985
  7. G. R. Rao, 'An accurate model for a depletion mode IGFET used as a load device' Solid-State Electron., vol. 21, pp. 711-714, May 1978 https://doi.org/10.1016/0038-1101(78)90002-3
  8. M.H. Kim, 'Three-dimensional numerical analysis of astronomical CCD image for X-ray or UV detection' Ph.D Thesis, University of Leicester, UK, 1995
  9. M.H. Kim and S.H. Lim, 'Three dimensional numerical simulation of buried channel MOSFETs,' ICEIC 2000 Proceedings of The 2000 International Conference on Electronics, Information and Communication, pp. 453- 456, August 9-11, 2000, Shenyang, China
  10. M.H. Kim and S.H. Lim, 'Three dimensional Characterizing Analysis of Astronomic CCDs with a Deep Depletion,'Proceedings of the Optical Society of Korea Summer Meeting 2000, pp. 228-229, August 17-18, 2000, JinJu, Korea
  11. C. Greenough, 'Three dimensional algoriths for a robust and efficient semiconductor simulator with parameter extraction: The EVEREST final report' Project Report, 1992
  12. M. J. Van der Tol and S. G. Chamberlain, 'Drain-induced barrier lowering in buried-channel MOSFETs' IEEE Trans. Electron Devices, v. ED-40, p. 741, 1993
  13. J. Janesick, T. Elliott, T. Daud, and D. Campbell, 'The CCD flash gate' SPIE Proc. SPIE Instrumentation in Astronomy VI, Solid State Imaging Arrays for Astronomy, Tucson, AZ, Mar. 1986
  14. P. K. Chaterjee and G.W.Taylor, 'Optimum scaling of buried-channel CCD's' IEEE Trans. Electron Devices, Vol. ED-27, Mar. 1980
  15. K. J. McCarthy and A. Wells, 'Measurement and simulation of X-ray quantum efficiency and energy resolution of large area CCDs between 0.3 and 10keV' SPIE Vol. 1743 EUV, X-RAY, and Gamma- Ray Instrumention for Astronomy III 1992
  16. N. Ballay and B. Baylac, 'Analytical modelling of depletion-mode MOSFET with short- and narrowchannel effects' IEE PROC., Vol. 128, Pt. I, No. 6, Dec. 1981
  17. M. H. kim, J. Fothergill and A. Holland, '3-dimensional numerical analysis of deep depletion charge-coupled devices' Proceedings of 1995 IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, 20-22 April, 1995, Data, Dana Point Resort, Dana Point, CA, USA