대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

부분 공핍형 SOI 게이트의 통계적 타이밍 분석

Statistical Timing Analysis of Partially-Depleted SOI Gates

  • 김경기 (노스이스턴대학교 전기컴퓨터공학과)
  • Kim, Kyung-Ki (Department of Electrical and Computer Engineering, Northeastern University)
  • 발행 : 2007.12.25
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초록

본 논문은 100 nm BSIMSOI 3.2 기술을 사용한 부분 공핍형 SOI (Partially-Depleted SOI: PD-SOI) 회로들의 정확한 타이밍 분석을 위한 새로운 통계적 특징화 방법과 추정 방법을 제안한다. 제안된 타이밍 추정 방법은 Matlab, Hspice, 그리고 C 언어로 구현되고, ISCAS 85 벤치마크 회로들을 사용해서 검증된다. 실험 편과는 Monte Carlo 시뮬레이션과 비교해 5 % 내의 에러를 보여준다.

This paper presents a novel statistical characterization for accurate timing analysis in Partially-Depleted Silicon-On-Insulator (PD-SOI) circuits in BSIMSOI3.2 100nm technology. The proposed timing estimate algorithm is implemented in Matlab, Hspice, and C, and it is applied to ISCAS85 benchmarks. The results show that the error is within 5% compared with Monte Carlo simulation results.

키워드

참고문헌

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