Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Low Power QPP Interleaver Address Generator Design Using The Periodicity of QPP

QPP 주기성을 이용한 저전력 QPP 인터리버 주소발생기 설계

  • Lee, Won-Ho (DL Team, KORNIC Systems Co., Ltd.) ;
  • Rim, Chong-Suck (Department of Computer Science and Engineering, Sognag University)
  • 이원호 ((주)코닉시스템 통신기술연구소) ;
  • 임종석 (서강대학교 컴퓨터공학과)
  • Published : 2008.12.25
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Abstract

The QPP interleaver has been gaining attention since it provides contention-free interleaving functionality for high speed parallel turbo decoders. In this paper we first show that the quadratic term $f_2x^2%K$ of $f(x)=(f_1x+f_2x^2)%K$, the address generating function, is periodic. We then introduce a low-power address generator which utilizes this periodic characteristic. This generator follows the conventional method to generate the interleaving addresses and also to save the quadratic term values during the first half of the first period. The saved values are then reused for generating further interleaved addresses, resulting in reduced number of logical operations. Power consumption is reduced by 27.38% in the design with fixed-K and 5.54% in the design with unfixed-K on average for various values of K, when compared with the traditional designs.

QPP 인터리버는 고속 병렬 터보 디코더에서 메모리 경합 없는 인터리빙 기능을 제공할 수 있어 주목을 받고 있다. 본 논문에서는 QPP 인터리버의 주소 생성 함수 $f(x)=(f_1x+f_2x^2)%K$의 이차항 $f_2x^2%K$가 아주 작은 주기를 갖는다는 것을 보이고, 이러한 주기성을 이용하여 설계한 저전력 주소 생성기를 소개한다. 소개한 주소 생성 방법에서는 처음 반주기 동안의 $f_2x^2%K$ 값들을 메모리에 저장하고 이 값들은 읽어 f(x)를 계산함으로써 $f_2x^2%K$값들의 계산 없이 주소를 생성한다. 이렇게 설계한 주소 생성기는 일반적인 방법에 의한 설계에 비하여 평균 5.54%(가변 K인 경우)와 27.38%(고정 K인 경우)의 전력 소모 절감 효과를 갖는다.

Keywords

References

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