• The Journal of Korean Institute of Communications and Information Sciences
• /
• 제18권10호
• /
• pp.1537-1545
• /
• 1993

In this paper, we design a pattern generator and a fault position detector to implement the proposed fault test algorithms which are Column Weight Sensitive Fault (CWSF) test algorithm and bit line decoder fault test algorithm for performing the Built-In Self Test(BIST) in RAM. A pattern generator consists of an address generator and a data generator. An address generator is divided into a row address generator for effective address and a column address generator for sequential and parallel addresses. A fault position detector is designed to determine whether full occurred or not and to find the position of the fault. We verify the implemented circuits by the simulation.

• Proceedings of the Korea Multimedia Society Conference
• /
• 한국멀티미디어학회 2003년도 춘계학술발표대회논문집
• /
• pp.14-18
• /
• 2003

This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT(Discrete Cosine Transform/Inverse Discrete Cosine Transform). For the real time process of image data, it is required that high speed operation and small size hardware In the proposed architecture, the area of hardware is reduced by using the DA(distributed arithmetic) method and applying the concepts of pipeline on the parallel architecture. As a results, the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared as the non-pipeline architecture. And the operation speed is improved about 50％ up. The design for the proposed pipeline architecture of DCT/IDCT is coded using VHDL.

• Proceedings of the Korea Institute of Convergence Signal Processing
• /
• 한국신호처리시스템학회 2003년도 하계학술대회 논문집
• /
• pp.262-267
• /
• 2003

At process of production according to development of accumulation degree of semi-conductor element, because functional mistake examination time required increases, is becoming big obstacle factor in cost-cutting. Studied pattern generator that generate pattern and address that is bundle enemy to process these controversial point effectively.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• 제45권12호
• /
• pp.83-88
• /
• 2008

The QPP interleaver has been gaining attention since it provides contention-free interleaving functionality for high speed parallel turbo decoders. In this paper we first show that the quadratic term $f_2x^2%K$ of $f(x)=(f_1x+f_2x^2)%K$, the address generating function, is periodic. We then introduce a low-power address generator which utilizes this periodic characteristic. This generator follows the conventional method to generate the interleaving addresses and also to save the quadratic term values during the first half of the first period. The saved values are then reused for generating further interleaved addresses, resulting in reduced number of logical operations. Power consumption is reduced by 27.38% in the design with fixed-K and 5.54% in the design with unfixed-K on average for various values of K, when compared with the traditional designs.

• Proceedings of the KIEE Conference
• /
• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
• /
• pp.924-927
• /
• 2003

In this paper, we design the memory tester chip set playing an important role in the memory tester as central parts. Memory tester has the sixteen inner instructions to control the test sequence and the address and data signals to DUT. These instructions are saved in memory with each chip such as sequence chip and address/data generator chip. Sequence chip controls the test sequence according to instructions saved in the memory. And Generator chip generates the address and data signals according to instructions saved in the memory, too.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• 제63권3호
• /
• pp.338-342
• /
• 2014

Energy storage is a key issue when integrating large amounts of intermittent and non-dispatchable renewable energy sources into electric power systems. To maintain the instantaneous power balance and to compensate for the influence of power fluctuations from renewable sources, flexible capability for power control is needed. Adjustable Speed Pumped Storage Power Generator is pumped storage unit that is adjustable for pump output adjustments as well as the highest efficiency operations because it has fast response time. In this paper we address the adjustable speed pumped storage power generator for frequency control against the intermittence of wind turbine output and calculate the appropriate capacity of adjustable speed pumped storage power generator.

• ETRI Journal
• /
• 제35권1호
• /
• pp.166-169
• /
• 2013

In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply-scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on-chip pseudorandom generator composed of an address-based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x-nm and 4x-nm NAND flash memory devices illustrate the effectiveness of our scheme. The results show that the error rate is reduced up to 86% compared to that of a conventional cycling scheme. Accordingly, the endurance phenomenon can be mitigated through analysis of interference that causes tech shrinkage.

• Proceedings of the IEEK Conference
• /
• 대한전자공학회 2002년도 ITC-CSCC -3
• /
• pp.1823-1826
• /
• 2002

On modern computer culture, the high quality data is required in multimedia systems. So, the technology of data compression fur data transmission is necessary now. This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT (Discrete Cosine Transform/Inverse Discrete Cosine Transform. In the proposed architecture, the area of hardware is reduced by using the DA (distributed arithmetic) method and applies the concepts of pipeline to the parallel architecture. As a result the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared with the non-pipeline architecture.

• Proceedings of the KIEE Conference
• /
• 대한전기학회 2004년도 심포지엄 논문집 정보 및 제어부문
• /
• pp.153-155
• /
• 2004

In this paper, we design the memory tester chip playing an important role in the memory tester as central parts. Memory tester has the sixteen inner instructions to control the test sequence and the address and data signals to DUT. These instructions are saved in memory with each block such as sequencer and pattern generator. Sequencer controls the test sequence according to instructions saved in the memory. And Pattern generator generates the address and data signals according to instructions saved in the memory, too. We can use these chips for various functional test of memory.

• Journal of information and communication convergence engineering
• /
• 제8권5호
• /
• pp.493-497
• /
• 2010

This paper address the problem of tracking multiple objects encountered in many situation in developing condensation algorithms. The difficulty lies on the fact that the implementation of condensation algorithm is not easy for the general users. We propose an automatic code generation program for condensation algorithm using MATLAB tool. It will help for general user who is not familiar with condensation algorithm to apply easily for real system. The merit of this program is that a general industrial engineer can easily simulate the designed system and confirm the its performance on the fly.