Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
권호 표지
DOI QR코드

DOI QR Code

Design of Floating-Point Multiplier for Mobile Graphics Application

모바일 그래픽스 응용을 위한 부동소수점 승산기의 설계

  • 최병윤 (동의대학교 컴퓨터공학과) ;
  • Published : 2008.03.31
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, two-stage pipelined floating-point multiplier (FP-MUL) is designed. The FP-MUL processor supports single precision multiplication for 3D graphic APIs, such as OpenGL and Direct3D and has area-efficient and low-latency architecture via saturated arithmetic, area-efficient sticky-bit generator, and flagged prefix adder. The FP-MUL has about 4-ns delay time under $0.13{\mu}m$ CMOS standard cell library and consists of about 7,500 gates. Because its maximum performance is about 250 MFLOPS, it can be applicable to mobile 3D graphics application.

본 논문에서는 2단 파이프라인 구조의 부동 소수점 승산기 회로를 설계하였다. 부동 소수점 승산기는 3차원 그래픽 API인 OpenGL과 Direct3D를 위한 단일 정밀도 곱셈 연산을 지원하며, 포화 연산, 면적 효율적인 점착(sticky) 비트 발생기 및 플래그 프리픽스 가산기를 결합하여, 면적 효율적이며 적은 파이프라인 지연 구조를 갖는다. 설계된 회로는 $0.13{\mu}m$ CMOS 표준 셀을 사용하여 합성 한 결과 약 4-ns의 지연시 간을 갖고 있으며, 약 7,500개로 구성된다. 설계된 부동 소수점 승산기의 최대 연산 성능은 약 250 MFLOPS이므로, 3차원 모바일 그래픽 분야에 효율적으로 적용 가능하다.

Keywords

References

  1. J.D. Foley, A. V. Dam, S. K. Feiner and J. F. Hughes, Computer Graphics : Principles and Practice, 2nd edition, Addison Wesley, Chapter 18, 1997
  2. Dave Astle and Dave Durnil, Opicro OpenGL ES Game Development, PTR, 2004.
  3. Kris Gray, Microsoft DirectX9 Programmable Pipeline, Microsoft Press 2004
  4. IEEE, ANSI/IEEE Standard 754-1985: IEEE Standard for Binary Floating-Point Arithmetic, IEEE Press, 1985
  5. Rubinfield, L.P, "A proof of the modified Booth's algorithm for multiplication," IEEE Transaction on Computer, vol.24, no.10, pp.1010-1015. October 1975 https://doi.org/10.1109/T-C.1975.224112
  6. M. Rooda, "Method to reduce the sign bit extension in a multiplier that uses the modified booth algorithm," Electronics Letters, vol 22, no.20, pp.1014-1015. 25h September, 1986 https://doi.org/10.1049/el:19860693
  7. C. S. Wallace, "A suggestion for parallel multipliers," IEEE Trans. Electron. Computer, no. EC-13, pp.14-17, Feb, 1964
  8. Mark R. Santoro, Gary Bewick and Mark A. Horowitz, "Rounding Algorithms for IEEE Multipliers", IEEE 9th Symposium on Computer Arithmetic, pp.176-183. 1989
  9. Robert K. Yu and Gregory B. Zyner, "167 MHz Radix-4 Floating Point Multiplier", IEEE 12th Symposium on Computer Arithmetic, 1 pp.149-154. 1995
  10. V.G. Oklobdjija, etal, "An algorithm and novel design of leading zero detector: comparison with logic synthesis," IEEE Transactions on VLSI, vol.2, pp.124-128, March 1994 https://doi.org/10.1109/92.273153
  11. J. Cortadella and J. M. Liaberia, "Evaluation of A+B=K conditions without carry propagation", IEEE Transaction on Computers, vol. 41, no.11, pp.1484-1488, Nov. 1992 https://doi.org/10.1109/12.177318
  12. Neil Burgess, "The flagged prefix adder and its applications in integer Arithmetic," Journal of VLSI Signal Processing, vol 31, pp.263-271, 2002 https://doi.org/10.1023/A:1015421507166
  13. G. Goto, A. Inoue, and T. Izawa, "A 4.1-ns Compact 54 $\times$ 54-b Multiplier Utilizing Sign-select Booth Encoders," IEEE JSSC, vol.32, no.11, pp.1676-1682, November, 1997.
  14. Yuyun Liao and David B. Roberts, "A High- Performance and Low-Power 32-bit Multiply-Accumulator Unit with Single-Instruction-Multiple-Data (SIMD) Feature," IEEE JSSC, vol.37, no.7, pp.926-931, August, 2004