JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

A Multiphase Compensation Method with Dynamic Element Matching Technique in Σ-Δ Fractional-N Frequency Synthesizers

  • Chen, Zuow-Zun (Department of Electrical Engineering and Graduate Institute of Electronics Engineering National Taiwan University) ;
  • Lee, Tai-Cheng (Department of Electrical Engineering and Graduate Institute of Electronics Engineering National Taiwan University)
  • Published : 2008.09.30
Download PDF
⟨ Previous Next ⟩

Abstract

A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.

Keywords

References

  1. T. A. Riley, M. Copeland, and T. Kwasniewski, "Delta-Sigma Modulation in Fractional-N Frequency Synthesis," IEEE J. Solid-State Circuits, Vol.28, pp.553-559, May 1993 https://doi.org/10.1109/4.229400
  2. B. De Muer and M. Steyaert, "A CMOS Monolithic $\Sigma\Delta$-Controlled Fractional-N Frequency Synthesizer DCS-1800," IEEE J. Solid-State Circuits, Vol.37, pp.835-844, July 2002 https://doi.org/10.1109/JSSC.2002.1015680
  3. W. Rhee, B. Song, and A. Ali, "A l.l GHz CMOS Fractional-N Frequency Synthesizer with A 3-b Third-Order $\Sigma\Delta$ Modulator," IEEE J. Solid-State Circuits, Vol.35, pp.1453-1460, Oct. 2000 https://doi.org/10.1109/4.871322
  4. M. Kozak and I. Kale, "Rigorous Analysis of Delta- Sigma Modulators for Fractional-N PLL Frequency Synthesis," IEEE Trans. Circuits Syst. I, Vol.51, pp.1148-1162, June 2004 https://doi.org/10.1109/TCSI.2004.829308
  5. E. Temporiti, G. Albasini, I. Bietti, R. Castello, and M. Colombo, "A 700-kHz Bandwidth $\Sigma\Delta$ Fractional Synthesizer With Spurs Compensation and Linearization Techniques for WCDMA Applications," IEEE J. Solid-State Circuits, Vol.39, pp. 1446-1454, Sep. 2004 https://doi.org/10.1109/JSSC.2004.831598
  6. S. Pamarti, L. Jansson, and I. Galton, "A Wideband 2.4-GHz Delta-Sigma Fractional-N PLL With 1-Mb/s In-Loop Modulation," IEEE J. Solid-State Circuits, Vol.39, pp.49-62, Jan. 2004 https://doi.org/10.1109/JSSC.2003.820858
  7. C.-H. Park, O. Kim, and B. Kim, "A 1.8 GHz Self- Calibrated Phase-Locked Loop with precise I/Q Matching," IEEE J. Solid-State Circuits, Vol.36, pp.777-783, May 2001 https://doi.org/10.1109/4.918915
  8. T. Riley and J. Kostamovaara, "A Hybrid Fractional- N Frequency Synthesizer," IEEE Trans. Circuits Syst. II, Vol.50, pp.176-180, Apr. 2003 https://doi.org/10.1109/TCSII.2003.809710
  9. C.-H. Heng, B.-B. Song, "A 1.8-GHz CMOS Fractional- N Frequency Synthesizer with Randomized Multiphase VCO," IEEE J. Solid-State Circuits, Vol.38, pp.848-854, June 2003 https://doi.org/10.1109/JSSC.2003.811872
  10. S. E. Meninger and M. H. Perrott, "A Fractional-N Frequency Synthesizer Architecture Utilizing a Mismatch Compensated PFD/DAC Structure for Reduced Quantization-Induced Phase Noise," IEEE Trans. Circuits Syst. II, Vol.50, pp.839-849, Nov. 2003 https://doi.org/10.1109/TCSII.2003.819114
  11. Y.-C. Yang, S.-A. Yu, Y.-H. Liu, T. Wang, and S.- S. Lu, "A Quantization Noise Suppression Technique for $\Delta\Sigma$ Fractional-N Frequency Synthesizers," IEEE J. Solid-State Circuits, vol. 41, pp.2500-2511, Nov. 2006 https://doi.org/10.1109/JSSC.2006.883325
  12. W. Rhee and A. Ali, "An On-Chip Phase Compensation Technique in Fractional-N Frequency Synthesis," in Proc. IEEE ISCAS, Vol.3, July 1999, pp.363-366
  13. R. K. Henderson and O. J. A. P. Nys, "An Analysis of Dynamic Element Matching Techniques in Sigma- Delta Modulation," in Proc. IEEE ISCAS, Vol.1, pp.231-234, May 1996
  14. R. K. Henderson and O. J. A. P. Nys, "Dynamic Element Matching Techniques with Arbitrary Noise Shaping Function," in Proc. IEEE ISCAS, Vol.1, pp.293-296, May 1996
  15. M. H. Perrott, M. D. Trott, and C. G. Sodini, "A Modeling Approach for $\Sigma-\Delta$ Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis," IEEE J. Solid-State Circuits, Vol.37, pp.839-849, Aug. 2002
  16. M. Kozak and I. Kale, "A Pipelined Noise Shaping Coder for Fractional-N Frequency Synthesis," IEEE Trans. Instrum. Meas., Vol.50, pp.1153-1161, Oct. 2001
  17. I. Galton, "Spectral Shaping of Circuit Errors in Digital-to-Analog Converters," IEEE Trans. Circuits Syst. II, Vol.44, pp.808-817, Oct. 1997 https://doi.org/10.1109/82.633435