JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Combined Clock and Data Recovery Circuit with Adaptive Cancellation of Data-Dependent Jitter

  • Published : 2008.09.30
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Abstract

A combined clock and data recovery (CDR) circuit with adaptive cancellation of data-dependent jitter (DDJ) is constructed in all-digital architecture which is amenable to deep submicron technology. The DDJ canceller uses an adaptive FIR filter to compen-sate for any unknown channel characteristic. The proposed CDR decreases jitter in the recovered clock since the DDJ canceller significantly cancels out incoming jitter caused by inter-symbol interference.

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References

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