Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A 12-kV HBM ESD Power Clamp Circuit with Latchup-Free Design for High-Voltage Integrated Circuits

고전압 집적회로를 위한 래치업-프리 구조의 HBM 12kV ESD 보호회로

  • Published : 2009.01.25
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Abstract

The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the operating voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD(ElectroStatic Discharge) power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a $0.35{\mu}m$ 3.3V/60V BCD(Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the operating voltage. Proposed power clamp operates safely because of the high holding voltage. From the measurement on the devices fabricated using a $0.35{\mu}m$ BCD Process, it was observed that the proposed ESD power clamp can provide 800% higher ESD robustness per silicon area as compared to the conventional clamps with a high-voltage diode.

고전압 소자에서 스냅백 이후의 유지 전압은 구동전압에 비해 매우 작아서 고전압 MOSFET이 ESD(ElecroStatic Discharge) 파워클램프로 바로 사용될 경우 래치업 문제를 일으킬 수 있다. 본 연구에서는 스택 바이폴라 소자를 이용하여 래치업 문제가 일어나지 않는 구조를 제안하였다. 제안된 구조에서는 유지 전압이 구동전압 보다 높으므로 래치업 문제가 발생하지 않으면서, 기존의 다이오드를 사용한 고전압 파워클램프에 비해 면적이 작으며, 내구성 측면에서 800% 성능향상이 있게 되었다. 제안된 구조는 $0.35{\mu}m$ 60V BCD(Bipolar-CMOS-DMOS) 공정을 사용하여 제작되었으며, TLP(Transmission Line Pulse) 장비로 웨이퍼-레벨 측정을 하였다.

Keywords

References

  1. G. Notermans, Z. Mrcarica, T Keller, H. van Zwol, T Smedes, and P. de Jong, 'Process and Design Optimization of a Protection Scheme Based on NMOSFETs with ESD Implant in 65nm and 45nm CMOS Technologies,' in Proc. EOS/ESD Symp., 2007, pp. 385-394
  2. 최진영, 임주섭, '소자 시율레이션을 이용한 ESD 보호용 NMOS 트랜지스터의 항복 특성 분석' 전자공학회논문지, 제 34권, SD편, 제 11호, pp.37-47, 1997년 11월
  3. K Chatty, R Gauthier, M. Abou-Khalil, D. Alvarez, and C. Russ 'Designing HV Active Clamps for HBM Robustness,' in Proc. EOS/ESD Symp., 2007, pp. 47-52
  4. J-H Lee, J-R Shih, C.-S. Tang, K -CO Liu, Y.-HWu, R-y' Shiue, T-C. Ong, y'-K Peng, and J -T Yue, 'Novel ESD protection structure with embedded SCR LDMOS for smart power technology,' in Proc. IEEE Int. Reliability Physics Symp., 2002, pp. 156-161
  5. V. De Heyn, G. Groeseneken, B. Keppens, M. Natarajan, L. Vacaresse, and G. Gallopyn, 'Design and analysis of new protection structures for smart power technology with controlled trigger and holding voltage,' in Proc. IEEE Int. Reliability Physics Symp., 2001, pp. 253-258
  6. Kawamoto, K, and Takahashi, I., 'An advanced no-snapback LDMOSFET with optimized breakdown characteristics of drain n-n+ diodes,' IEEE transactions on electron devices, v.51 no.9, 2004, pp.1432-1440 https://doi.org/10.1109/TED.2004.833591
  7. R Lewis and J Minor, 'Simulation of a system level transient-induced latchup event,' in Proc. EOS.ESD Symp., 1994, pp. 193-199
  8. Ming-Dou Ker and Kun-Hsien Lin, "The Impact of Low-Holding-Voltage Issue in High-Voltage CMOS Technology and the Design of Latchup-Free Power-Rail ESD Clamp Circuit for LCD Driver ICs," IEEE Jounal of Solid-State Circuits, vol. 40, no. 8, pp.1751-1759, Aug. 2005 https://doi.org/10.1109/JSSC.2005.852046
  9. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981
  10. M.-D. Ker and K -H Lin, 'Double snapback characteristics in high voltage nMOFETs and the impact to on-chip ESD protection design,' IEEE Electron Device Lett., vol. 25, no. 9, pp. 640-642, Sep.2004 https://doi.org/10.1109/LED.2004.833372
  11. ESD-STM5.l-2001, Standard Test Method For Component Level HBM Tester Waveform Verification Procedure; Electrostatic Discharge Association, Tome NY