The Journal of the Korea institute of electronic communication sciences (한국전자통신학회논문지)

Korea Institute of Electronic Communication Science (한국전자통신학회)
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Synthesis and application of Pt and hybrid Pt-$SiO_2$ nanoparticles and control of particles layer thickness

Pt 나노입자와 Hybrid Pt-$SiO_2$ 나노입자의 합성과 활용 및 입자박막 제어

  • 최병상 (조선대학교 금속재료공학과)
  • Received : 2009.10.18
  • Accepted : 2009.12.03
  • Published : 2009.12.31
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Abstract

Pt nanoparticles with a narrow size distribution (dia. ~4 nm) were synthesized via an alcohol reduction method and used for the fabrication of hybrid Pt-$SiO_2$ nanoparticles. Also, the self-assembled monolayer of Pt nanoparticles (NPs) was studied as a charge trapping layer for non-volatile memory (NVM) applications. A metal-oxide-semiconductor (MOS) type memory device with Pt NPs exhibits a relatively large memory window. These results indicate that the self-assembled Pt NPs can be utilized for NVM devices. In addition, it was tried to show the control of thin-film thickness of hybrid Pt-$SiO_2$ nanoparticles indicating the possibility of much applications for the MOS type memory devices.

Pt 나노입자의 합성과 이를 이용한 hybrid Pt-$SiO_2$ 나노입자의 합성을 성공적으로 수행하였으며, self-assembled Pt nanoparticles monolayer를 charge trapping layer로 활용하는 metal-oxide-semiconductor(MOS) type memory의 한 예로 non-volatile memory(NVM)의 응용을 보임으로써 나노입자의 활용 가능성을 보이고, 또한, hybrid Pt-$SiO_2$ 나노입자 박막 층의 제어를 통한 MOS type memory device에의 보다 더 넓은 활용 가능성을 보이고자 하였다.

Keywords

References

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