JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

A Low Vth SRAM Reducing Mismatch of Cell-Stability with an Elevated Cell Biasing Scheme

  • Received : 2009.12.02
  • Published : 2010.06.30
Download PDF
⟨ Previous Next ⟩

Abstract

A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (${\sigma}Vth$) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-nm CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to $6{\sigma}$ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.

Keywords

References

  1. T. Suzuki, H. Yamauchi, Katsuji Satomi, and Hironori Akamatsu, “A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Bising Scheme,” IEEE Custom Integrated Circuits Conference, pp.35-38, Sep. 2007.
  2. Y. Komatsu, K. Ishibashi, M. Yamamoto, T. Tsukada, K. Shimazaki, M. Fukazawa, and M. Nagata, “Substrate-Noise and random-Variations Reduction with Self-Adjusted Forward Body Bias,” IEEE Custom Integrated Circuits Conference, pp.35-38, Sep. 2005
  3. G. Tsutui, K. Tsunoda, N. Kariya, Y. Akiyama, T. Abe, S. Maruyama, T. Fukase, M. Suzuki, Y. Yamagata, and K. Imai, “Reduction of Vth variation by work function optimization for 45-nm node SRAM cell,” Symp.VLSI Technology., Digest of Technical Papers, pp.158-159, June 2008.
  4. R. Tsuchiya, N.Sugii, Takashi Ishigaki, Y. Morita, H. Yoshimoto, K. Torii and Shin’ichiro Kimura, “Low Voltage (Vdd-0.6V) SRAM Operation Achived by Reduced Threshold Voltage Variability in SOTB (Silicon on Thin BOX),” Symp.VLSI Technology., Digest of Technical Papers, pp.150-151, June 2009.
  5. K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, “A 3-GHz 70Mb SRAM in 65nm CMOS Technology with Integrated Column-Based Dynamic Power Supply,” IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp.474-475, February 2005
  6. M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K. Yanagisawa, and T. Kawahara, “Low-Power Embedded SRAM Modules with Expanded Margins for Writing,” IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 480-481, February 2005.
  7. T. Suzuki, H. Yamauchi, Y. Yamagami, K. Satomi and Hironori Akamatsu, “A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write Disturbed Accesses,” IEEE Journal of Solid-State Cirsuits, vol. 43, No. 9, pp.2109-2119, Sep. 2008. https://doi.org/10.1109/JSSC.2008.2001872
  8. J. Pile, C. Adams, T. Christensen, S. Cottier, S. Ehrenreich, F. Kono, D. Nelson, O. takahashi, S. Tokito, O. Torreiter, O. wagner and D. Wendel, “Implementation of the CELL Broadband Engine isn a 65nm SOI Technology Featuring Dual Supply SRAM Arrays Supporting 6GHz at 1.3V,” IEEE International Solid-State Circuits Conference, Digest of Technical Paper, pp.322-323, February 2007.
  9. R. Joshi, R. Houle, K. Batson, D. Rodko, P. Petel, W. Houtt, R. Franch, Y. Chan, D. Plass, S. Wilson and P. Wang, “6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM,” Digest of Technical Papers, pp.250-251, June 2007.
  10. Y.H.Chen, W.M. Chan, S.Y. chou, H.J. Liao, H.Y. Pan, J.J. Wu, C.H. Lee, S.M. Yang, Y.C. Liu and H. Yamauchi, “A 0.6V 45nm Adaptive Dual-Rail SRAM Compiler Circuit Design for Lower VDD_min VLSIs,” Symp.VLSI Circuits., Digest of Technical Papers, pp.210-211, June 2008.
  11. S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, M. Igarashi, M. Takeguchi, H. Kawashima, H. Makino, Y. Ymaguchi, K. Tsukamoto, M. Inuishi, K. Ishibashi and H. shinohara, “A 65nm SoC Embedded 6T-SRAM Design for Manufacturaing with Read and Write Cell Stabilizing Circuits,” Symp.VLSI Circuits., Digest of Technical Papers, pp.20-21, June 2006.
  12. M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Ohbayashi S. Imaoka, H. Makino, Y. Yamagami, S. Ishikura, T. Terano, T. Oashi, K. Hashimoto, A. Sebe, G. Okazaki, K. Satomi, H. Akamatsu and H. Shinohara, “A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations,” IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp.326-327, February 2007.
  13. O. Hirabayashi, A. Kawasumi, Y. Takeyama, K. Kushida, T. Sasaki, A. Katayama, G. Fukano, Y. Fujimura, T. Nakazato, Y. Shizuki, N. Kushiyama, and Y. Yabe, “A Process-Variation-Tolerant Dual-Power-Supply SRAM with $0.179{\mu}m^2$ Cell in 40nm CMOS Using Level-Programmable Wordline Driver,” IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp.458-459, February 2009
  14. K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K.Usui, T. Kawamura, N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino and H. Shinohara, “A 45-nm Single-port and Dual-port SRAM family with Robust Read/Write Stabilizing Circuitry under DVFS Environment,” Symp.VLSI Circuits., Digest of Technical Papers, pp.212-213, June 2008
  15. K. Nii, Y. Masuda, M. Yabuuchi, Y. Tshikamoto, S. Ohbayashi, S. Imaoka, M. Igarashi, K. Tomita, N. Tsuboi, H. Makino, K. Ishibashi and H. Shinohara, “A 65 nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC,” Symp.VLSI Circuits., Digest of Technical Papers, pp.130-131, June 2006.