JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Comparative Study on the Structural Dependence of Logic Gate Delays in Double-Gate and Triple-Gate FinFETs

  • Kim, Kwan-Young (School of Electrical Engineering, Kookmin University) ;
  • Jang, Jae-Man (School of Electrical Engineering, Kookmin University) ;
  • Yun, Dae-Youn (School of Electrical Engineering, Kookmin University) ;
  • Kim, Dong-Myong (School of Electrical Engineering, Kookmin University) ;
  • Kim, Dae-Hwan (School of Electrical Engineering, Kookmin University)
  • Received : 2010.02.28
  • Published : 2010.06.30
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Abstract

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

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