Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
권호 표지

Thermal Cycling and High Temperature Storage Reliabilities of the Flip Chip Joints Processed Using Cu Pillar Bumps

Cu Pillar 플립칩 접속부의 열 싸이클링 및 고온유지 신뢰성

  • Kim, M.Y. (Materials Science and Engineering, Hongik University) ;
  • Lim, S.K. (Materials Science and Engineering, Hongik University) ;
  • Oh, T.S. (Materials Science and Engineering, Hongik University)
  • 김민영 (홍익대학교 신소재공학과) ;
  • 임수겸 (홍익대학교 신소재공학과) ;
  • 오태성 (홍익대학교 신소재공학과)
  • Received : 2010.09.02
  • Accepted : 2010.09.14
  • Published : 2010.09.30
Download PDF
⟨ Previous Next ⟩

Abstract

For the flip chip joints processed using Cu pillar bumps and Sn pads, thermal cycling and high temperature storage reliabilities were examined as a function of the Sn pad height. With increasing the height of the Sn pad, which composed of the flip chip joint, from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance of the flip chip joint decreased from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$. Even after thermal cycles of 1000 times ranging from $-45^{\circ}C$ to $125^{\circ}C$, the Cu pillar flip chip joints exhibited the contact resistance increment below 12% and the shear failure forces similar to those before the thermal cycling test. The contact resistance increment of the Cu pillar flip chip joints was maintained below 20% after 1000 hours storage at $125^{\circ}C$.

Cu pillar 범프와 Sn 패드로 구성된 플립칩 접속부를 형성한 후, Sn 패드의 높이에 따른 Cu pillar 플립칩 접속부의 열 싸이클링 및 고온유지 신뢰성을 분석하였다. Cu pillar 플립칩 접속부를 구성하는 Sn 패드의 높이가 5 ${\mu}m$에서 30 ${\mu}m$로 증가함에 따라 접속저항이 31.7 $m{\Omega}$에서 13.8 $m{\Omega}$로 감소하였다. $-45^{\circ}C{\sim}125^{\circ}C$ 범위의 열 싸이클을 1000회 인가한 후에도 Cu pillar 플립칩 접속부의 접속저항의 증가가 12% 이하로 유지되었으며, 열 싸이클링 시험전과 거의 유사한 파괴 전단력을 나타내었다. $125^{\circ}C$에서 1000 시간 유지시에도 Cu pillar 플립칩 접속부의 접속저항의 증가가 20% 이하로 유지되었다.

Keywords

References

  1. J. Y. Choi and T. S. Oh, "Flip Chip Process by Using the Cu- Sn-Cu Sandwich Joint Structure of the Cu Pillar Bumps", J. Microelectron. Packag. Soc., 16(4), 9 (2009).
  2. J. H. Choi, K. Y. Lee, S. W. Jun, Y. H. Kim and T. S. Oh, "Contact Resistance of the Chip-on-glass Bonded 48Sn-52In Solder Joint", Mater. Trans., 46, pp.1042-1046 (2005). https://doi.org/10.2320/matertrans.46.1042
  3. J. W. Wan, W. J. Zhang and D. J. Bergstrom, "Recent Advances in Modeling the Underfill Process in Flip-chip Packaging", Microelectron. J., 38(1), 67 (2007). https://doi.org/10.1016/j.mejo.2006.09.017
  4. T. Braun, K. F. Becker, M. Koch, V. Bader, R. Aschenbrenner and H. Reichl, "High-temperature Reliability of Flip Chip Assemblies", Microelectron. Reliab., 46(1), 144 (2006). https://doi.org/10.1016/j.microrel.2005.06.004
  5. K. N. Tu and K. Zeng, "Under Bump Metallurgy Study for Pb-free Bumping", Mater. Sci. Eng., 34, 1 (2001). https://doi.org/10.1016/S0927-796X(01)00029-8
  6. J. H. Lau, "Low Cost Flip Chip Technologies", pp.511, McGraw-Hill, New York (2000).
  7. J. H. Lau, "Low Cost Flip Chip Technologies", pp.183, McGraw-Hill, New York (2000).
  8. B. Banijamali, I. Mohammed and P. Savalia, "Crack Growth- Resistant Interconnects for High-Reliability Microelectronics" 57th Electron. Comp. Technol. Conf., IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2008).
  9. A. Keigler, B. Wu, J. Zhang and Z. Liu, "Pattern Effects on Electroplated Copper Pillars", Inter. Wafer-level Packag. Conf. (2006).
  10. G. T. Lim, B. J. Kim, K. Lee, J. Kim, Y. C. Joo and Y. B. Park, "Temperature Effect on Intermetallic Compound Growth Kinetics of Cu Pillar/Sn Bumps", J. Electron. Mater., 38(11), 2228 (2009). https://doi.org/10.1007/s11664-009-0922-0
  11. T. Wang, F. Tung, L. Foo and V. Dutta, "Studies on a Novel Flip-Chip Interconnect Structure-Pillar Bump", Proc. Electron. Comp. Technol. Conf., pp.945-949 (2001).
  12. J. Y. Choi, M. Y. Kim, S. K. Lim and T. S. Oh, "Flip Chip Process for RF Packages Using Joint Structures of Cu and Sn Bumps", J. Microelectron. Packag. Soc., 16(4), 67 (2009).
  13. Li-Rong Zheng, Xinzhong Duo, M. Shen, W. Michielsen and H. Tenhunen, "Cost and Performance Trade-off Analysis in Radio and Mixed-Signal System-on-Package Design", IEEE Trans. Adv. Packag., 27(2), 364 (2004). https://doi.org/10.1109/TADVP.2004.828818
  14. A. Chandrasekhar, E. Beyne, W. De Raedt and B. Nauwelaers, "Accurate RF Electrical Characterization of CSPs Using MCM-D Thin Film Technology", IEEE Trans. Adv. Packag., 27(1), 203 (2004). https://doi.org/10.1109/TADVP.2004.824945
  15. E. Beyne, "Multilayer Thin-Film Technology Enabling Technology for Solving High-Density Interconnect and Assembly Problems", Nuclear Inst. Methods Phys. Res. A, 509(1-3), 191 (2003). https://doi.org/10.1016/S0168-9002(03)01570-5
  16. K. M. Chen and T. S. Lin, "Copper Pillar Bump Design Optimization for Lead Free Flip-Chip Packaging", J. Mater. Sci. Mater. Electron., 21(3), 278 (2009).
  17. C. W. Tan, Y. C. Chan and N. H. Yeung, "Effect of Autoclave Test on Anisotropic Conductive Joints", Microelectron. Reliab., 43(2), 279 (2003). https://doi.org/10.1016/S0026-2714(02)00293-7
  18. J. H. Zhang, Y. C. Chan, M. O. Alam and S. Fu, "Contact Resistance and Adhesion Performance of ACF Interconnections to Aluminum Metallization", Microelectron. Reliab., 43(8), 1303 (2003). https://doi.org/10.1016/S0026-2714(03)00165-3
  19. Y. T. Hsieh, "Reliability and Failure Mode of Chip-on-film with Non-conductive Adhesive", Proc. 4th Int. Symp. Electron. Mater. Packag. (EMAP), Kaohsiung, Taiwan, 157, IEEE Component, Packaging & Manufacturing Technology (2002).
  20. G. T. Lim, B. J. Kim, K. W. Lee, M. J. Lee, Y. C. Joo and Y. B. Park, "Study on the Intermetallic Compound Growth and Interfacial Adhesion Energy of Cu Pillar Bump", J. Microelectron. Packag. Soc., 15(4), 17 (2008).