A Wideband ${\Delta}{\Sigma}$ Frequency Synthesizer for T-DMB/DAB/FM Applications in $0.13{\mu}m$ CMOS

T-DMB/DAB/FM 수신기를 위한 광대역 델타시그마 분수분주형 주파수합성기

  • Shin, Jae-Wook (Department of Wireless Communications Engineering, Kwangwoon University) ;
  • Shin, Hyun-Chol (Department of Wireless Communications Engineering, Kwangwoon University)
  • Received : 2010.09.30
  • Accepted : 2010.10.29
  • Published : 2010.12.25

Abstract

This paper presents a wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer for a multi-band single chip CMOS RFIC transceivers. A wideband VCO utilizes a 6-bit switched capacitor array bank for 2340~3940 MHz frequency range. VCO frequency calibration circuit is designed for optimal capacitor bank code selection before phase locking process. It finishes the calibration process in $2{\mu}s$ over the whole frequency band. The LO generation block has selectable multiple division ratios of ${\div}2$, ${\div}16$, and ${\div}32$ to generate LO I/Q signals for T-DMB/DAB/FM Radio systems in L-Band (1173~1973 MHz), VHF-III (147~246 MHz), VFH-II (74~123 MHz), respectively. The measured integrated phase noise is quite low as it is lower than 0.8 degree RMS over the whole frequency band. Total locking time of the ${\Delta}{\Sigma}$ frequency synthesizer including VCO frequency calibration time is less than $50{\mu}s$. The wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer is fabricated in $0.13{\mu}m$ CMOS technology, and it consumes 15.8 mA from 1.2 V DC supply.

본 논문은 다중대역 송수신기 CMOS RFIC 단일 칩을 위한 광대역 델타시그마 분수분주형 주파수합성기에 관한 것이다. 광대역 VCO의 LC Tank에 6-bit Switched Capacitor Array Bank를 작용하여 2340~3940 MHz의 출력주파수 범위를 가지도록 하였으며, 위상동기 전 Capacitor Bank Code를 선택하기위한 VCO Frequency Calibration 회로는 전체 주파수대역에서 $2{\mu}s$이하로 보정을 마치는 뛰어난 성능을 보여준다. 광대역 VCO로부터 T-DMB/DAB/FM Radio의 LO 신호를 생성하기 위해 선택 가능한 다중분주비 ${\div}2$, ${\div}16$, ${\div}32$를 가지는 LO 신호 발생기는 L-Band (1173 ~ 1973 MHz), VHF-III (147 ~ 246 MHz), VFH-II (74~123 MHz)에서 I/Q신호를 생성한다. Integrated Phase Noise는 전체 대역에서 0.8 degree RMS 이하로 측정되어 매우 낮은 위상잡음을 보여주었다. 또한, VCO Frequency Calibration 시간을 포함하는 주파수합성기의 전체 동기시간은 $50{\mu}s$ 이하로 측정되었다. 이 광대역 델타시그마 분수분주형 주파수합성기는 $0.13{\mu}m$ CMOS공정으로 제작되었으며, 1.2 V 전원전압에서 15.8 mA의 전류를 소모한다.

Keywords

References

  1. A. Kral, F. Behbahani, A. A. Abidi, "RF-CMOS Oscillators with Switched Tuning," in Proc. IEEE Custom Integr. Cir. Conf., May 1998, pp. 555-558
  2. W. B. Wilson, U. -K. Moon, K. R. Lakshmikumar, and L. Dai, "A CMOS Self-Calibrating Frequency Synthesizer," IEEE J. Solid-State Circuits, vol. 35, no. 10, pp 1437-1444, Oct. 2000. https://doi.org/10.1109/4.871320
  3. Behzad Razavi, "Challenges in the Design of Cognitive Radios," in Proc. IEEE Custom Integrated Circuits Conference, San Jose, CA., Sep. 2009, pp 391-398.
  4. Seungsoo Kim and Hyunchol Shin, "A 0.6-2.7GHz Semidynamic Frequency Divide-by-3 Utilizing Wideband RC Polyphase Filter in $0.18\;{\mu}m$ CMOS," IEEE Microwave and Wireless Components Letters, vol. 18, no. 10, pp.701-703, Oct. 2008. https://doi.org/10.1109/LMWC.2008.2003478
  5. Jaewook Shin, Jongsik Kim, Seungsoo Kim, and Hyunchol Shin, A Delta-Sigma Fractional-N Frequency Synthesizer for Quad-Band Multi-Standard Mobile Broadcasting Tuners in $0.18\;{\mu}m$ CMOS," Journal of Semiconductor Technology and Science, vol. 7, no. 4, pp.267-273, Dec. 2007. https://doi.org/10.5573/JSTS.2007.7.4.267
  6. Jae-Shin Lee, Min-Sun Keel, Shin-Il Lim, and Suki Kim, "Charge pump with perfect current matching characteristics in phase-locked loops," Electronics Letters, vol. 36, no. 23, pp.1907-1908, Nov. 2000. https://doi.org/10.1049/el:20001358
  7. Jongsik Kim, Jaewook Shin, Seungsoo Kim, and Hyunchol Shin, "A Wideband CMOS LC VCO with Linearized Coarse Tuning Characteristics," IEEE Transactions on Circuits and Systems-II, vol. 55, no. 5, pp.399-403, May 2008. https://doi.org/10.1109/TCSII.2007.914896
  8. H. -I. Lee, J. -K. Cho, K. -S. Lee, I. -C. Hwang, T. -W. Ahn, K. -S. Nah, and B. -H. Park, "A SD Fractional-N Frequency Synthesizer Using a Wide-Band Integrated VCO and a Fast AFC Technique for GSM/GPRS/WCDMA Applications," IEEE J. Solid-State Circuits, vol. 39, no. 7, pp.1164-1169, July 2004.
  9. M., Marutani, H. Anbutsu, M. Kondo, N. Shirai, H. Yamazaki, and Y. Watanabe, "An 18mW 90 to 770MHz Synthesizer with Agile Auto-Tuning for Digital TV Tuners," in IEEE Int. Solid-State Cir. Conf. Dig. Tech. Papers, pp. 192-193, Feb. 2006.
  10. T. -H. Lin, and Y. -J. Lai, "An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL," IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 340-349, Feb. 2007. https://doi.org/10.1109/JSSC.2006.889360
  11. J. Lee, K. Kim, J. Lee, T. Jang, and S. Cho, "A 480-MHz to 1-GHz Sub-picosecond Clock Generator with a Fast and Accurate Automatic Frequency Calibration in $0.13\;{\mu}m$ CMOS," in Proc. IEEE Asian Solid-State Cir. Conf., Nov. 2007, pp. 67-70
  12. I. Vassiliou, Kostis Vavelidis, Nikos Haralabidis, Aris Kyranas, Yiannis Kokolakis, Stamatis Bouras, George Kamoulakos, Charalambos Kapnistis, Spyros Kavadias, Nikos Kanakaris, Emmanouil Metaxakis, Christos Kokozidis, and Hamed Peyravi, "A 65 nm CMOS Multistandard, Multiband TV Tuner for Mobile and Multimedia Applications," IEEE Journal of Solid-State Circuits, vol. 43, no. 7, pp. 1522-1533, Jul. 2008. https://doi.org/10.1109/JSSC.2008.923721
  13. Supisa Lerstaveesin, Manoj Gupta, David Kang, and Bang-Sup Song, "A 48-860 MHz CMOS Low-IF Direct-Conversion DTV Tuner," IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2013-2024, Sep. 2008. https://doi.org/10.1109/JSSC.2008.2001900