무연 솔더 접합부을 갖는 플립칩에서의 언더필 및 범프 피치 변화에 의한 열 피로 수명 예측 해석

Simulation of Thermal Fatigue Life Prediction of Flip Chip with Lead-free Solder Joints by Variation in Bump Pitch and Underfill

  • 김성걸 (서울산업대학교 기계 설계자동화공학부) ;
  • 김주영 (서울산업대학교 에너지 환경 대학원 Nano/IT 공학과)
  • 투고 : 2009.04.01
  • 심사 : 2009.10.11
  • 발행 : 2010.04.15

초록

This paper describes the thermal fatigue life prediction models for 95.5Sn-4.0Ag-0.5Cu solder joints of Flip chip package considering Under Bump Metallurgy(UBM). A 3D Finite element slice model was used to simulate the viscoplastic behavior of the solder. For two types of solder bump pitches, simulations were analyzed and the effects of underfill packages were studied. Consequently, it was found out that solder joints with underfill had much better fatigue life than solder joints without underfill, and solder joints with $300{\mu}m$ bump pitch had a longer thermal fatigue life than solder joints with $150{\mu}m$ bump pitch. Through the simulations, flip chip with lead-free solder joints should be designed with underfill and a longer bump pitch.

키워드

참고문헌

  1. Yoon, J. W., Kim, J. W., Koo, J. M., Ha, S. S., Noh, B. I., Moon, W. C., Moon, J. H., and Jung, S. B., 2007, "Flip-chip Bonding Technology and Reliability of Electronic Packaging," Journal of KWJS, Vol. 25, No.2, pp. 108-117.
  2. Shin, Y. E., Kim, Y. S., Kim, J, M., and Chop, M. G., 2004, "The Thermal Fatigue Analysis and Life Evaluation of Solder Joint for Package using Darveaux," Journal of KWS, Vol. 22, No. 6, pp. 36-42.
  3. Shin, K H., Kim, H. T., and Jang, D. Y., 2007, "An Analysis on the Thermal Shock Characteristics of Pb-free Solder Joints and UBM in Flip Chip Packages," Journal of KSMTE, Vol.16 No. 5, pp. 134-139.
  4. Shin, K. H. and Kim, J. H., 2007, "Solid Modeling of UBM and IMC Layers in Flip Chip Packages," Journal of KSMTE, Vol. 16, No. 6, pp. 181-186.
  5. Darveaux, R., Islam, M. N., Singh, N., and Suhling, J. C., 2004, "Model for BGA and CSP Reliability in Automotive Underhood Application," IEEE Transaction on Components and Packaging Technologies, Vol. 27, No.3, pp. 585-593. https://doi.org/10.1109/TCAPT.2004.831824
  6. Ng, H. S., Tee, T. Y., Goh, K. Y., Luan, J. E., Reinikainen, T., Hussa, E., and Kujala, ,A., 2005, "Absolute and Relative Fatigue Life Prediction Methodology for Virtual Qualification and Design Enhancement of Lead-free BGA", IEEE Electronic Components and Technology Conf., pp. 1282-1291.
  7. Zhang, L., Sitaraman, R, Patwardhan, V., Nguyen, L., and Kelkar, N., 2003, "Solder Joint Reliability Model with Modified Darveaux's Equations for the micro SMD Wafer Level-Chip Scale Package Family," IEEE Electronic Components and Technology Conf., pp. 572-577.
  8. Darveaux, R, 2000, "Effect of Simulation Methodology on Solder Joint Crack Growth Correlation," Proc. 50th ECTC, pp. 1048-1063.
  9. Tseng, S. C., Chen, R. S., and Lio, C. C., 2006, "Stress Analysis of Lead-free Solders with Under Bump Metallurgy in a Wafer Level Chip Scale Package," International Journal of Advanced Manufacturing Technology, Vol. 31, No. 1-2, pp. 1-9. https://doi.org/10.1007/s00170-005-0165-z