A Study of the Threshold Voltage of a Symmetric Double Gate Type MOSFET

대칭형 이중 게이트 MOSFET에 대한 문턱전압 연구

  • Received : 2010.10.12
  • Accepted : 2010.12.15
  • Published : 2010.12.31

Abstract

In this thesis, in order to a equivalent circuit-analytical study for a symmetric double gate type MOSFET, we slove analytically the 2D Poisson's equation in a a silicon body. To solve the threshold voltage in a symmetric double gate type MOSFET from the derived expression for the surface potential which the two-dimensional potential distribution of a symmetric double gate type MOSFET is assumed approximately. This thesis can use short and long channel in a silicon body we introduce a new the threshold voltage model in a symmetric double gate type MOSFET and measure it the distance about the range of channel length up to 0.1 [${\mu}m$].

본 논문에서는 대칭형 이중 게이트 MOSFET의 회로해석에 대한 등가모델을 제시하고자 해석적 모델을 연구하였다. 본 연구의 해석적 모델에 사용된 방법은 2차원 포아송 방정식의 해를 가정하여 표면 전위 관계식을 유도하여 실리콘 몸체 내의 전위분포를 풀어 드레인 전압 변화에 대한 문턱전압 관계식을 도출하였다. 단채널 및 장채널 실리콘 채널에서 모두 해석이 가능한 해석적 모델을 적용 가능하도록 하기 위해 MOSFET의 채널 길이에 따른 제한된 지수함수를 적용함으로써 수백 나노미터까지 해석이 가능한 대칭형 이중 게이트 MOSFET 해석적 모델을 연구하였다.

Keywords

References

  1. S. P. Sinha, A. Zaleski, D. E. Ioannou, "Investigation of carrier generation in fully depleted enhancement and accumulation mode SOI MOSFET's," IEEE Trans. Electron Devices, vol. 42, no. 12, pp. 2413 - 2416, Dec. 1994.
  2. Ni. Pei, Weiping A. V. Kammula, B. A. Minch, E. C. Kan, "A physical compact model of DG MOSFET for mixed-signal circuit applications-part I : model description," IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2135 - 2143, Dec. 2004.
  3. Weimin Zhang, Fossum, J. G, Mathew, L, Yang Du, "Physical insights regarding design and performance of independent-gate FinFETs," IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 2198 - 2206, Oct. 2005. https://doi.org/10.1109/TED.2005.856184
  4. K. K. Young, "Short-channel effect in fully depleted SOI MOSFETs," IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 399 - 402, Feb. 1989. https://doi.org/10.1109/16.19942
  5. Y. Omura, "A simple model for short-channel effects of a buried-channel MOSFET on the buried insulator," IEEE Trans. Electron Devices, vol. 29, no. 11, pp. 1749-1755, Nov. 1982. https://doi.org/10.1109/T-ED.1982.21021
  6. A. Dasgupta, S. K. Lahiri, "A two-dimensional analytical model of threshold voltages of short-channel MOSFETs with Gaussian-doped channels," IEEE Trans. Electron Devices, vol. 35, no. 3, pp. 390-392, Mar. 1988. https://doi.org/10.1109/16.2468
  7. Yu Tian, Ru Huang, Xing Zhang, Yangyuan Wang, "A novel nanoscaled device concept: quasi-SOI MOSFET to eliminate the potential weaknesses of UTB SOI MOSFET," IEEE Trans. Electron Devices, vol. 52, no. 4, pp. 561 - 568, Apr. 2005. https://doi.org/10.1109/TED.2005.844737
  8. T. J. Cunningham, R. C. Gee, E. R. Fossum, S. M. Baier, "Deep cryogenic noise and electrical characterization of the complementary heterojunction field-effect transistor (CHFET)," IEEE Trans. Electron Device Letters, vol. 41, no. 6, pp. 888-894, Nov. 1994. https://doi.org/10.1109/16.293298
  9. K. W. Terrill, C. U. Hu, P. K. Ko, "An Analytical Model for the Channel Electric Field in MOSFET's with Graded-Drain Structures," IEEE Trans. Electron Device Letters, vol. 5, no. 11, pp. 440-442, Nov. 1984. https://doi.org/10.1109/EDL.1984.25980
  10. Ge. Lixin, J. G. Fossum, "Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 2, pp. 287 - 294, Feb. 2002. https://doi.org/10.1109/16.981219
  11. K. N. Ratnakumer, J. D. Meindle, "Short-channel MOST threshold Voltage Model," IEEE J. of Solid-state Circuits, vol. SC-17, pp. 937-947, Oct. 1982.