한국생산제조학회지 (Journal of the Korean Society of Manufacturing Technology Engineers)

  • 제20권2호
  • /
  • Pages.193-201
  • /
  • 2011
  • /
  • 2508-5093(pISSN)
  • /
  • 2508-5107(eISSN)
한국생산제조학회 (The Korean Society of Manufacturing Technology Engineers)
권호 표지

Sn-3.0Ag-0.5Cu 및 Sn-1.0Ag-0.5Cu 조성의 솔더 볼을 갖는 플립칩에서의 보드레벨 낙하 해석

Board-Level Drop Analyses having the Flip Chips with Solder balls of Sn-3.0Ag-0.5Cu and Sn-1.0Ag-0.5Cu

  • 김성걸 (서울과학기술대학교 기계설계자동화공학부)
  • 투고 : 2010.11.12
  • 심사 : 2011.01.31
  • 발행 : 2011.04.15
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

Recently, mechanical reliabilities including a drop test have been a hot issue. In this paper, solder balls with new components which are Sn-3.0Ag-0.5Cu and Sn-1.0Ag-0.5Cu-0.05N are introduced, and board level drop test for them are conducted under JEDEC standard in which the board with 15 flip chips is dropped as 1,500g acceleration during 0.5ms. The drop simulations are studied by using a implicit method in the ANSYS LS-DYNA, and modal analysis is made. Through both analyses, the solder balls with new components are evaluated under the drop. It is found that the maximum stress of each chip is occurred between the solder ball and the PCB, and the highest value among the maximum stresses in the chips is occurred on the chip nearest to fixed holes on the board in the drop tests and simulations.

키워드

참고문헌

  1. Yoon, J. W., Kim, J. W., Koo, J. M., Ha, S. S., Noh, B. I., Moon, W. C., Moon, J. H., and Jung, S. B., 2007, "Flip-Chip Bonding Technology and Reliability of Electronic Packaging", Journal of KWJS, Vol. 25, No. 2, pp. 108-117.
  2. Lee, S. B., Kim, J. M., Lee, S. H., and Shin, Y. E., 2007, "A Study on Reliability Improvement for Flip Chip Package", Spring Conference of KSMTE, pp. 529-535.
  3. Tee, Y., Luan, J., Ng, H. S., Lim, C. K., Pek, E., and Zhong, Z., 2004, "Advanced Experimental and Simulation Techniques for Analysis of Dynamic Responses during Drop Impact", 54th Electronic Components and Technology Conference, pp.1088-1094.
  4. Mattila, T. T., Marjamaki, P., and Kivilahti, J. K., 2006, "Reliability of CSP Interconnctions under Mechanical Shock Loading Conditions", IEEE Transaction on Components and Packaging Technologies, Vol. 29, No. 4, pp.787-795. https://doi.org/10.1109/TCAPT.2006.885948
  5. Luan, J., Tee, Y. Tee, Zhang, X., and Hussa, E., 2005, "Solder Joint Failure Modes, Mechanisms, and Life Prediction Models of IC Packages under Board Level Drop Impact", IEEE 6th International Conference on Electronic Packaging Technology, pp. 382-388.
  6. Kim, S. K., Kim, H, J., Lim, S. Y., Kim, S. Y., Yang, I. Y, and An, E. J., 2010, "Dynamic Reliability Assesment of Solder Balls on the Design Parameters of Flip Chips", Autumn Conference of KSMTE, pp. 149-153.
  7. JEDEC standard. 2003, Board Level Drop Test Method of Components for Handheld Electronic Products, JESD22-B111, JEDEC Solid State Technology Association, Arlington in USA.