Journal of the Korea Society of Computer and Information (한국컴퓨터정보학회논문지)

Korean Society of Computer Information (한국컴퓨터정보학회)
권호 표지
DOI QR코드

DOI QR Code

Thermal Pattern Comparison between 2D Multicore Processors and 3D Multicore Processors

2차원 구조와 3차원 구조에 따른 멀티코어 프로세서의 온도 분석

  • Choi, Hong-Jun (School of Electronics and Computer Engineering, Chonnam National University) ;
  • Ahn, Jin-Woo (School of Electronics and Computer Engineering, Chonnam National University) ;
  • Jang, Hyung-Beom (Division of Computer and Communication Engineering, Korea University) ;
  • Kim, Jong-Myon (School of Electrical Engineering, University of Ulsan) ;
  • Kim, Cheol-Hong (School of Electronics and Computer Engineering, Chonnam National University)
  • 최홍준 (전남대학교 전자컴퓨터공학부) ;
  • 안진우 (전남대학교 전자컴퓨터공학부) ;
  • 장형범 (고려대학교 컴퓨터전파통신공학부) ;
  • 김종면 (울산대학교 컴퓨터정보통신공학부) ;
  • 김철홍 (전남대학교 전자컴퓨터공학부)
  • Received : 2010.10.13
  • Accepted : 2011.05.04
  • Published : 2011.09.30
Download PDF
⟨ Previous Next ⟩

Abstract

Unfortunately, in current microprocessors, increasing the frequency causes increased power consumption and reduced reliability whereas it improves the performance. To overcome the power and thermal problems in the singlecore processors, multicore processors has been widely used. For 2D multicore processors, interconnection is regarded as one of the major constraints in performance and power efficiency. To reduce the performance degradation and the power consumption in 2D multicore processors, 3D integrated design technique has been studied by many researchers. Compared to 2D multicore processors, 3D multicore processors get the benefits of performance improvement and reduced power consumption by reducing the wire length significantly. However, 3D multicore processors have serious thermal problems due to high power density, resulting in reliability degradation. Detailed thermal analysis for multicore processors can be useful in designing thermal-aware processors. In this paper, we analyze the impact of workload distribution, distance to the heat sink, and number of stacked dies on the processor temperature. We also analyze the effects of the temperature on overall system performance. Especially, this paper presents the guideline for thermal-aware multicore processor design by analyzing the thermal problems in 2D multicore processors and 3D multicore processors.

동작 주파수의 증가는 싱글코어 프로세서의 성능을 크게 향상시키는 반면 전력 소모 증가와 높은 온도로 인한 신뢰성 저하 문제를 유발하고 있다. 최근에는 싱글코어 프로세서의 한계점을 극복하기 위한 대안으로 멀티코어 프로세서가 주로 사용되고 있다. 하지만, 멀티코어 프로세서를 2차원 구조로 설계하는 경우에는 내부 연결망에서의 전송 지연 현상으로 인해 프로세서의 성능 향상이 제약을 받고 있다. 내부 연결망에서의 전송 지연을 줄이기 위한 방안으로 멀티코어 프로세서를 3차원 구조로 설계하는 연구가 최근 큰 주목을 받고 있다. 2차원 구조 멀티코어 프로세서와 비교하여 3차원 구조 멀티코어 프로세서는 성능 향상과 전력 소모 감소의 장점을 지닌 반면, 높은 전력 밀도로 인해 발생된 발열 문제가 프로세서의 신뢰성을 위협하는 문제가 되고 있다. 3차원 멀티코어 프로세서에서 발생되는 발열 문제에 대한 상세한 분석이 제공된다면, 프로세서의 신뢰성을 확보하기 위한 연구 진행에 큰 도움이 될 것으로 기대된다. 그러므로 본 논문에서는 3차원 멀티코어 프로세서의 온도에 밀접하게 연관된 요소인 작업량, 방열판과의 거리, 그리고 적층되는 다이의 개수와 온도 사이의 관계를 자세히 살펴보고 높은 온도가 프로세서의 성능에 미치는 영향 또한 분석하고자 한다. 특히, 2차원 구조 멀티코어 프로세서와 3차원 구조 멀티코어 프로세서에서의 온도 문제를 함께 분석함으로써, 온도 측면에서 효율적인 프로세서 설계를 위한 가이드라인을 제시하고자 한다.

Keywords

References

  1. V. Agarwal, M.S. Hrishikesh, S.W. Keckler and D. Burger, "Clock rate versus IPC: the end of the road for conventional microarchitectures," In Proceedings of the 27th International Symposium on Computer Architecture, pp. 248-259, 2000.
  2. K. Olukotun, L. Hammond and J. Laudon, "Chip Multipr ocessor Architecture:Techniques to Improve Throughput and Latency," Morgan&Claypool, 2007.
  3. D. M. Tullsen, S. Eggers, H. M. Levy, "Simultaneous multithreading: Maximizing on-chip parallelism," In proceedings of the 22rd international symposium on Computer Architecture, pp. 392-403, 1995.
  4. C. Isci, A. Buyuktosunoglu, C.Y. Cher, P. Bose and M, Martonosi, "An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget", In Proceedings of 39th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 347-358, 2006.
  5. R. Kumar, V. Zyuban and D.M. Tullsen, "Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling," In Proceedings of The 32nd International Symposium on Computer Architecture, pp. 408-419, 2005.
  6. B. Black, D.W. Nelson, C. Webb and N. Samra, "3D Pro cessing Technology and its Impact on IA32 Microprocessors," In Proceedings of IEEE International Conference on Computer Design, pp. 316-318, 2004.
  7. D. Nelson, C. Webb, D. McCauley, K. Raol, J. R. II, J. DeVale and B. Black, "A 3D Interconnect Methodology Applied to iA32-class Architectures for Performance Improvements through RC Mitigation," In Proceedings of the 21st International VLSI Multilevel Interconnection Conference, pp. 78-83, 2004.
  8. S. W. Yoon, D. W. Yang, J. H. Koo, M. Padmanathan and F. Carson, "3D TSV processes and its assembly/Packaging technology," In Proceedings of IEEE International Conference on 3D System Integration, pp. 1-5, 2009.
  9. S.Das and A.Chandrakasan, "Timing, energy, and thermal performance of three-dimensional integrated circuits," In proceedings of Great Lakes Symposium on VLSI, pp. 338-343, 2004.
  10. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sank aranarayanan and D. Tarjan, "Temperature-Aware Microarchitecture," In proceedings of the 30th International Symposium on Computer Architecture, pp. 2-13, 2003.
  11. K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy and D. Tarjan, "Temperature-Aware Microarchitecture: Modeling and Implementation," Transactions on Architecture and Code Optimization, Vol. 1, No. 1, pp. 94-125, 2004. https://doi.org/10.1145/980152.980157
  12. S. Imand K. Banerjee, "Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs," In proceedings of International IEDM Technical Digest, pp. 727-730, 2000.
  13. International Technology Roadmap for Semiconductors, avail able at http://public.itrs.net.
  14. Jichuan Chang and Gurindar S. Sohi, "Cooperative Caching for Chip Multiprocessors," In Proceedings of the 33rd international symposium on Computer Architecture, pp. 264-276, 2006.
  15. R. E. Kessler, "The Alpha 21364 microprocessor," Journal of IEEE MICRO, Vol. 19, Issue 2, pp. 24-36, 1996.
  16. D. Brooks, V. Tiwari and M. Martonosi, "Wattch: A Fra mework for Architectural-level Power Analysis and Optimizations," In Proceedings of the 27th Annual International Symposium on Computer Architecture, pp. 83-94, 2000.
  17. W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan and S. Ghosh, "HotSpot: A Compact Thermal Modeling Method for CMOS VLSI Systems," IEEE Transactions on VLSI Systems, 2006.
  18. J. L. Henning, "SPEC CPU2000: measuring cpu performance in the new millennium," IEEE Computer, Vol. 33, no. 7, pp. 28-35, 2000. https://doi.org/10.1109/2.869367
  19. S. Chung and K. Skadron, "Using On-Chip Event Counters For High-Resolution, Real-Time Temperature Measur ement," In Proceedings of Thermal and Thermomechanical Phenomena in Electronics Systems, pp. 114-120, 2006.
  20. D. Brooks and M. Martonosi, "Dynamic Thermal Man agement for High-Performance Microprocessors," In Proceedings of the 7th International Symposium on High-Performance Computer Architecture, pp. 171-182, 2001.
  21. K. Choi, R. Soma and M. Pedram, "Dynamic voltage and frequency scaling based on workload decomposition," In Proceedings of the 2004 international symposium on Low power electronics and design, pp. 174-179, 2004.
  22. L. Benini, G. De Micheli, E. Macii, M. Poncino and R. Scarsi, "Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers," In Transactions on Design Automation of Electronic Systems (TODAES), Vol. 4, no. 4, pp. 351-375, 1999. https://doi.org/10.1145/323480.323482
  23. A. K. Coskun, T. S. Rosing, J. Ayala, D. Atienza and Y. Leblebici, "Dynamic thermal management in 3D multicore architectures," In proceedings of Design Automation and Test in Europe (DATE), pp. 1410-1415, 2009.