ETRI Journal

  • 제33권5호
  • /
  • Pages.752-758
  • /
  • 2011
  • /
  • 1225-6463(pISSN)
  • /
  • 2233-7326(eISSN)
한국전자통신연구원 (Electronics and Telecommunications Research Institute)
권호 표지
DOI QR코드

DOI QR Code

A CMOS 5.4/3.24-Gbps Dual-Rate CDR with Enhanced Quarter-Rate Linear Phase Detector

  • 투고 : 2010.10.04
  • 심사 : 2011.01.13
  • 발행 : 2011.10.31
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a 'Mode' switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under $2^{31}-1$ bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm${\times}$1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 ${\mu}m$ CMOS process.

키워드

참고문헌

  1. VESA, DisplayPort Standard, v1.2, Jan. 2010.
  2. Y.S. Seo et al., "A 5-Gbit/s Clock-and-Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-um CMOS Technology," IEEE Trans. Circuits Syst., vol. 56, no. 1, Jan. 2009, pp. 6-10.
  3. S. Byun et al., "A 10-Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector," IEEE J. Solid-State Circuits, vol. 41, no. 11, Nov. 2006, pp. 2566-2576. https://doi.org/10.1109/JSSC.2006.883334
  4. J. Savoj and B. Razavi, "A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector," IEEE J. Solid-State Circuits, vol. 36, no. 5, May 2001, pp. 761-767. https://doi.org/10.1109/4.918913
  5. D. Rennie and M. Sachdev, "A 5-Gb/s CDR Circuit with Automatically Calibrated Linear Phase Detector," IEEE Trans. Circuits Syst., vol. 55, no. 3, Apr. 2008, pp. 796-803. https://doi.org/10.1109/TCSI.2008.916400
  6. H.S. Muthali, T.P. Thomas, and I.A. Young, "A CMOS 10-Gb/s SONET Transceiver," IEEE J. Solid-State Circuits, vol. 39, no. 7, July 2004, pp. 1026-1033. https://doi.org/10.1109/JSSC.2004.829935
  7. M. Hsieh and G.E. Sobelman, "Architectures for Multi-Gigabit Wire-Linked Clock and Data Recovery," IEEE Circuit Syst. Mag., vol. 8, 2008, pp. 45-57. https://doi.org/10.1109/MCAS.2008.930152
  8. L. Henrickson and D. Shen, "Low-Power Fully Integrated 10- Gb/s SONET/SDH Transceiver in 0.13-${\mu}m$ CMOS," IEEE J. Solid State Circuit, vol. 38, no. 10, Oct. 2003, pp. 1595-1601. https://doi.org/10.1109/JSSC.2003.817586
  9. R. Yang et al., "A 155.52 Mbps-3.125 Gbps Continuous-Rate Clock and Data Recovery Circuit," IEEE J. Solid-State Circuit, vol. 41, no. 6, June 2006, pp. 1380-1390. https://doi.org/10.1109/JSSC.2006.874328

피인용 문헌

  1. A 3.8-GHz highly linear LC-VCO without a varactor device vol.10, pp.5, 2011, https://doi.org/10.1587/elex.10.20130038
  2. A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO vol.13, pp.3, 2011, https://doi.org/10.5573/jsts.2013.13.3.185
  3. 단일 에지 이진위상검출기를 사용한 저 지터 클록 데이터 복원 회로 설계 vol.17, pp.4, 2013, https://doi.org/10.7471/ikeee.2013.17.4.544
  4. A low jitter clock and data recovery with a single edge sensing Bang-Bang PD vol.11, pp.7, 2011, https://doi.org/10.1587/elex.11.20140088