JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

Thermal Aware Buffer Insertion in the Early Stage of Physical Designs

  • Received : 2012.01.30
  • Published : 2012.12.31
Download PDF
⟨ Previous Next ⟩

Abstract

Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results.

Keywords

References

  1. C. Tsai and S. M. Kang, "Cell-level placement for improving substrate thermal distribution," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 19, No. 2, pp. 253-266, Feb., 2000. https://doi.org/10.1109/43.828554
  2. K. Sundaresan and N. R. Mahapatra, "Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses," Quality Electronic Design, 2008, ISQED 2008. 9th International Symposium on, 17-19, pp.118-122, Mar., 2008.
  3. A. H. Ajami, K. Banerjee, and M. Pedram, "Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 24, No. 6, pp. 849-861, Jun., 2005. https://doi.org/10.1109/TCAD.2005.847944
  4. A. H. Ajami, K. Banerjee, and M. Pedram, "Analysis of substrate thermal gradient effects on optimal buffer insertion," Computer Aided Design, 2001, ICCAD 2001. IEEE/ACM International Conference on , pp. 44-48, 2001.
  5. K. Sundaresan and N. R. Mahapatra, "An analysis of timing violations due to spatially distributed thermal effects in global wires," DAC 2007, In proceedings of the 44th annual Conference on, 4-8, pp. 515-520, Jun., 2007.
  6. P. Saxena, N. Menezes, P. Cocchini, and D. A. Kirkpatrick, "Repeater scaling and its impact on CAD," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 23, No. 4, pp. 451- 463, Apr., 2004. https://doi.org/10.1109/TCAD.2004.825841
  7. G. Van and P. P. P. Lukas, "Buffer placement in distributed RC-tree networks for minimal Elmore delay," Circuits and Systems, 1990., IEEE International Symposium on, Vol. 2, pp. 865-868, May, 1990.
  8. M. Kim, B. Ahn, Jaehwan Kim, B. Lee, and Jongwha Chong, "Thermal Aware Timing Budget for Buffer Insertion in Early Stage of Physical Design," 2012 IEEE International Symposium on Circuits & Systems Proceedings, May, 2012.
  9. K. Athikulwongse, X. Zhao, and S. K. Lim, "Buffered clock tree sizing for skew minimization under power and thermal budgets," Design Automation Conference, 2010, 15th Asia and South Pacific, 18-21, pp. 474-479, Jan., 2010.
  10. C. Alpert and A. Devgan, "Wire segmenting for improved buffer insertion," Design Automation Conference, 1997, Proceedings of the 34th, 9-13, pp. 588-593, Jun., 1997.
  11. S. N. Adya and I. L. Markov, "Fixed-outline Floorplanning : Enabling Hierarchical Design," VLSI Systems, 2003, IEEE Transaction on, Vol. 11, No. 12, pp. 1120-1135, Dec., 2003.
  12. Wei Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, K, and M. R. Stan, "HotSpot: a compact thermal modeling methodology for early-stage VLSI design," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 14, no. 5, pp. 501-513, May 2006. https://doi.org/10.1109/TVLSI.2006.876103
  13. http://ptm.asu.edu/.
  14. W. Shi and Z. Li, "A fast algorithm for optimal buffer insertion," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 24, No. 6, pp. 879- 891, Jun., 2005. https://doi.org/10.1109/TCAD.2005.847942
  15. M.-S. Jang, Design Technology team, System LSI, Samsung Electronics Co., LTD, Private Communication, Jul. 2012.