JSTS:Journal of Semiconductor Technology and Science

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Efficient Implementation of Single Error Correction and Double Error Detection Code with Check Bit Pre-computation for Memories

  • Received : 2012.04.30
  • Published : 2012.12.31
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Abstract

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

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References

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  2. Compact and power efficient SEC-DED codec for computer memory pp.1432-1858, 2019, https://doi.org/10.1007/s00542-019-04366-7