JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring

  • Yoo, Byoung-Joo (Department of Electrical Engineering and Computer Science, Seoul National University) ;
  • Song, Ho-Young (Department of Electrical Engineering and Computer Science, Seoul National University) ;
  • Chi, Han-Kyu (Department of Electrical Engineering and Computer Science, Seoul National University) ;
  • Bae, Woo-Rham (Department of Electrical Engineering and Computer Science, Seoul National University) ;
  • Jeong, Deog-Kyoon (Department of Electrical Engineering and Computer Science, Seoul National University)
  • Received : 2012.06.08
  • Published : 2012.12.31
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Abstract

A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth. The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weight-adjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-nm CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9-28 inch Nelco4000-6 microstrips at 4-7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only $0.152mm^2$ and consumes 69.8 mW, while the rest of the receiver occupies $0.297mm^2$ and consumes 56.0 mW at the 7- Gb/s data-rate and supply voltage of 1.35 V.

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References

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