한국생산제조학회지 (Journal of the Korean Society of Manufacturing Technology Engineers)

  • 제21권2호
  • /
  • Pages.225-231
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  • 2012
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  • 2508-5093(pISSN)
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  • 2508-5107(eISSN)
한국생산제조학회 (The Korean Society of Manufacturing Technology Engineers)
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언더필을 고려한 Sn-1.0Ag-0.5Cu 조성의 솔더볼을 갖는 플립칩에서의 보드레벨 낙하 및 진동해석

Board Level Drop Simulations and Modal Analysis in the Flip Chips with Solder Balls of Sn-1.0Ag-0.5Cu Considering Underfill

  • 김성걸 (서울과학기술대학교 기계시스템디자인공학과) ;
  • 임은모 (서울과학기술대학교 대학원 기계시스템디자인공학과)
  • 투고 : 2012.03.08
  • 심사 : 2012.03.27
  • 발행 : 2012.04.15
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초록

Drop simulations of the board level in the flip chips with solder joints have been highlighted for years, recently. Also, through the study on the life prediction of thermal fatigue in the flip chips considering underfill, its importance has been issued greatly. In this paper, dynamic analysis using the implicit method in the Finite Element Analysis (FEA) is carried out to assess the factors effecting on flip chips considering underfill. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard is modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. Modal analysis is simulated to find out the relation between drop impact and vibration of the board system.

키워드

참고문헌

  1. Tee, Y., Luan, J., Ng, H. S., Lim, C. K., Pek, E., and Zhong, Z., 2004, "Advanced Experimental and Simulation Techniques for Analysis of Dynamic Responses during Drop Impact," 54th Electronic Components and Technology Conference, pp. 1088-1094.
  2. Mattila, T. T., Marjamaki, P., and Kivilahti, J. K., 2006, "Reliability of CSP Interconnctions under Mechanical Shock Loading Conditions," IEEE Transaction on Components and Packaging Technologies, Vol. 29, No. 4, pp. 787-795. https://doi.org/10.1109/TCAPT.2006.885948
  3. Kim, S. K., and Lim, E. M., 2011, "Dynamic Reliability of Board Level by Changing the Design Parameters of Flip Chips," KSMTE, Vol. 20, No. 5, pp. 559-563.
  4. Kim, S. K., and Kim, J. Y., 2010, "Simulation of Thermal Fatigue Life Prediction of Flip Chip with Lead-free Solder Joints by Variation in Bump Pitch and Underfill," KSMTE, Vol. 19, No. 2, pp. 157-162.
  5. JEDEC standard, 2003, Board Level Drop Test Method of Components for Handheld Electronic Products, JESD22-B111.
  6. Kim, S. K., Kim, H. J., Lim, S. Y, Kim, S. Y., Yang, I. Y., and An, E. J., 2010, "Dynamic Reliability Assesment of Solder Balls on the Design Parameters of Flip Chips," KSMTE, Fall Conference, pp. 149-153.
  7. Kim, S. K., 2011, "Board-Level Drop Analyses having the Flip Chips with Solder balls of Sn-3.0Ag-0.5Cu and Sn-1.0Ag-0.5Cu," KSMTE, Vol. 20, No. 2, pp. 193-201.
  8. Kim, S. K., Kim, K. L., Bae, J. G., Park, S. H. and Lee, D. G., 2009, "Dynamic Analysis of Flip Chips with Solder Balls with Two Different Compositions," KSPE, Fall Conference, pp. 207-208.

피인용 문헌

  1. Prediction of Impact Life Time in Solder Balls of the Board Level Flip Chips by Drop Simulations vol.23, pp.3, 2014, https://doi.org/10.7735/ksmte.2014.23.3.237
  2. Prediction of the Impact Lifetime for Board-Leveled Flip Chips by Changing the Design Parameters of the Solder Balls vol.24, pp.1, 2015, https://doi.org/10.7735/ksmte.2015.24.1.117