Packet Detection and Frequency Offset Estimation/Correction Architecture Design and Analysis for OFDM-based WPAN Systems

OFDM-기반 WPAN 시스템을 위한 패킷 검출 및 반송파 주파수 옵셋 추정/보정 구조 설계 및 분석

  • Back, Seung-Ho (School of Information and Communication Engineering, Inha University) ;
  • Lee, Han-Ho (School of Information and Communication Engineering, Inha University)
  • 백승호 (인하대학교 정보통신공학부) ;
  • 이한호 (인하대학교 정보통신공학부)
  • Received : 2011.06.13
  • Accepted : 2012.06.21
  • Published : 2012.07.25

Abstract

This paper presents packet detection, frequency offset estimation architecture and performance analysis for OFDM-based wireless personal area network (WPAN) systems. Packet detection structure is used to find the start point of a packet exactly in WPAN system as the correlation value passes the constant threshold value. The applied autocorrelation structure of the algorithm can be implemented simply compared to conventional packet detection algorithms. The proposed frequency offset estimation architecture is designed for phase rotation process structure, internal bit reduction to reduce hardware size and the frequency offset adjustment block to reduce look-up table size unlike the conventional structure. If the received signal can be compensated by estimated frequency offset through the correction block, it can reduce the impact on the frequency offset. Through the performance result, the proposed structure has lower hardware complexity and gate count compared to the conventional structure. Thus, the proposed structure for OFDM-based WPAN systems can be applied to the initial synchronization process and high-speed low-power WPAN chips.

본 논문은 mmWave OFDM-기반 WPAN 시스템을 위한 패킷 검출과 주파수 옵셋 추정 및 보정 구조를 제안하고 성능 분석 결과를 보여준다. 패킷 검출 블록은 반복된 훈련 심볼의 자기상관 관계를 이용하고 상관된 값이 일정 문턱 값을 넘을 때 패킷 시작점을 검출하는데 사용된다. 적용한 자기상관 알고리즘 구조는 기존의 패킷검출에 사용한 알고리즘에 비해 간단하게 하드웨어를 구현 할 수 있다. 주파수 옵셋 추정 구조는 기존구조와는 다른 위상 천이 처리 블록, 하드웨어 사이즈를 줄여주는 내부비트 줄임 블록 및 look-up table의 사이즈를 줄인 주파수 옵셋 조정 블록을 설계하였다. 추정된 주파수 옵셋 값은 설계한 보정 블록을 통해 수신 신호를 보정함으로써 주파수 옵셋에 대한 영향을 줄일 수 있다. 설계 검증툴을 이용한 성능 분석 결과 제안된 구조는 하드웨어 구현복잡도가 감소함을 보여 주었고 기존구조에 비하여 게이트수가 감소함을 보였다. 따라서 제안된 구조는 OFDM-기반 WPAN 시스템의 초기 동기화 과정에 적용 될 수 있고 고속 저전력 WPAN칩에 사용 될 수 있다.

Keywords

References

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