DOI QR코드

DOI QR Code

A 12-b Asynchronous SAR Type ADC for Bio Signal Detection

  • Lim, Shin-Il (Department of Electronics Engineering, Seokyeong University) ;
  • Kim, Jin Woo (Department of Electronics Engineering, Seokyeong University) ;
  • Yoon, Kwang-Sub (Department of Electronics Engineering, Inha University) ;
  • Lee, Sangmin (Department of Electronics Engineering, Inha University)
  • Received : 2012.08.01
  • Accepted : 2013.01.09
  • Published : 2013.04.30

Abstract

This paper describes a low power asynchronous successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for biomedical applications in a 0.35 ${\mu}m$ CMOS technology. The digital-to-analog converter (DAC) uses a capacitive split-arrays consisting of 6-b main array, an attenuation capacitor C and a 5-b sub array for low power consumption and small die area. Moreover, splitting the MSB capacitor into sub-capacitors and an asynchronous SAR reduce power consumption. The measurement results show that the proposed ADC achieved the SNDR of 68.32 dB, the SFDR of 79 dB, and the ENOB (effective number of bits) of 11.05 bits. The measured INL and DNL were 1.9LSB and 1.5LSB, respectively. The power consumption including all the digital circuits is 6.7 ${\mu}W$ at the sampling frequency of 100 KHz under 3.3 V supply voltage and the FoM (figure of merit) is 49 fJ/conversion-step.

Keywords

References

  1. B. P. Ginsburg and A. P. Chandrakasan, "An Energy-Efficient Charge Recycling Approach for a SAR Converter With Capacitive DAC," in Proc. IEEE Int. Sym. Circuits and System, 2005, vol. 1, pp. 184-187.
  2. Michael D. Scott, Bernhard E. Boser and Kristofer S. J. Pister, "An Ultralow-Energy ADC for Smart Dust," IEEE J. Solid-state Circuits, vol. 38, pp. 1123-1129, July 2003. https://doi.org/10.1109/JSSC.2003.813296
  3. Pieter Harpe, Cui Zhou, Xiaoyan Wang, Guido Dolmans, and Harmke de Groot, "A 30fJ/Conversion-Step 8b 0-to-10 MS/s Asynchronous SAR ADC in 90nm CMOS", ISSCC Dig. Tech Papers, pp.387-389, Feb. 2010
  4. Peng Zhu Yan, Chi-Hang Chan, Maloberti F., "A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS", IEEE Journal of Solid-state circuits, pp.1111-1121, June., 2010
  5. Sin Sai-Weng, Ding Li, Zhu Yan, Maloberti Franco, "An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H", ESSCIRC, pp.218- 221, Sept., 2010
  6. Hao-Chiao Hong and Guo-Ming Lee, "A 65- fJ/Conversion-Step 0.9-V 200kS/s Rail-to-Rail 8-bit Successive Approximation ADC", IEEE Journal of Solid-state circuits, Vol. 42, no.10, Oct. 2007.
  7. M. Miyahara, M. Asada, D. Paik and A. Matsuzawa, "A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADC," Proc. of ASSCC, pp. 269-272, Nov. 3-5, 2008

Cited by

  1. Analog Front-End Circuit Design for Bio-Potential Measurement vol.50, pp.11, 2013, https://doi.org/10.5573/ieek.2013.50.11.130
  2. A 0.16㎟ 12b 30MS/s 0.18um CMOS SAR ADC Based on Low-Power Composite Switching vol.53, pp.7, 2016, https://doi.org/10.5573/ieie.2016.53.7.027