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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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A Broadband Digital Step Attenuator with Low Phase Error and Low Insertion Loss in 0.18-${\mu}m$ SOI CMOS Technology

  • Cho, Moon-Kyu (Department of Electronic Engineering, Kwangwoon University) ;
  • Kim, Jeong-Geun (Department of Electronic Engineering, Kwangwoon University) ;
  • Baek, Donghyun (School of Electrical Engineering, Chung-Ang University)
  • Received : 2012.08.06
  • Accepted : 2013.01.11
  • Published : 2013.08.01
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Abstract

This paper presents a 5-bit digital step attenuator (DSA) using a commercial 0.18-${\mu}m$ silicon-on-insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T-type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than $2.5^{\circ}$ and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is $0.93mm{\times}0.68mm$, including pads. To the best of the authors' knowledge, this is the first demonstration of a low phase error DC-to-20-GHz SOI DSA.

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References

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